• Reduced project length from 24 to 19 months
• Modeling time condensed from 6 months to 1 month
• Product cost reduced by 12% through increased analysis
• Architecture refinement completed before implementation started reduced rework
• Verification effort reduced through early architecture validation

Modeling using VisualSim

• Model constructed using VisualSim pre-built modeling libraries
• Traffic created using Traffic Reader block and randomizer
• All hardware components defined using VisualSim Transaction-Level, cycle-accurate blocks
• Total number of IP blocks instantiated in the model = 200
• Software tasks generated as instruction sequence using Software Generator module

• Graphical environment provided a wrapper for instantiating SystemC C++ classes.
• Over 6500 lines of SystemC code to define the system
• Custom statistics required to be generated

Key Findings using VisualSim

• Latency exceeded threshold for READ and WRITE operations for certain schedulings
• Validated Bus utilization based on different input video traffic scenarios
• Computed number of pipeline stages to minimize processor Wait state
• Designed custom L2 cache algorithm for lower Bus rates