Mirabilis Design provides performance analysis and architecture exploration solution for the design of electronics and real-time software. The product, VisualSim, is a graphical modeling and simulation environment. Models of the proposed system are constructed by engineers in VisualSim using parameterized modeling library and C/C++/Java/SystemC/Verilog/VHDL. Designers and architects can conduct trade-off studies by varying parameter values, executing different input traffic stimulus and modifying the system configuration including the topology. The parameterized libraries contain traffic generators, statistics viewers, processing flows, resources, architecture components and application-specific functions. The outputs from VisualSim are a highly optimized design, executable specification and virtual platform to verify implementation.
The examples contained on the pages linked below demonstrates the model construction and trade-off possibilities in VisualSim. User can experience VisualSim by clicking on the model links. The leads to a new Browser page that instantiate a pre-built VisualSim model to display and execute within the Web Browser. The user can click on an icon in the graphical model to view the parameters. Click on "GO" button to start the simulation. Double-click on names (model parameters) in the model view, change the values and execute the simulations.
VisualSim Architect, the desktop application, was used to construct these models. Over 250 additional models are shipped with VisualSim. To experience model-based design using VisualSim, request for an Evaluation or send us an email.
Java
Runtime Environment is reqired to
view the Demonstrations,
To
download click here
Parallel
Processor
The Processor Array Model investigates
the effects of generating fixed
tasks, sending them via a serial
virtual connection to nine processors,
processing the task and sending
to a task collector block.
L1,
L2, L3- Cache Model- Queuing Model
Analyze response time and cache
utilization based on various cache
hit-ratios and cache speeds.
L1,
L2, L3- Refined Cache Model- Queuing
Model
Adds processor stall, additional
frequency and traffic parameters
knobs, waveform plots and variable
traffic generation.
Dual
Processor Server
Optimize an enterprise server with
dual processors and bus architecture
for component sizing and arbitration
algorithms.
VME
BUS
The VME Bus Model can support different
standards through the proper selection
of parameters in the model
Information
Appliance Platform Model
Explore the latency and quality
of a video stream on a PDA with
a smart media, wireless link. Combines
functional and performance analysis.
Shared
Bus Architecture
Models a shared bus, similar to
3GIO and PCI-X.
