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Home | Demonstrations | Networking & Protocols

      Networking & Protocols

Mirabilis Design provides performance analysis and architecture exploration solution for the design of electronics and real-time software. The product, VisualSim, is a graphical modeling and simulation environment. Models of the proposed system are constructed by engineers in VisualSim using parameterized modeling library and C/C++/Java/SystemC/Verilog/VHDL. Designers and architects can conduct trade-off studies by varying parameter values, executing different input traffic stimulus and modifying the system configuration including the topology. The parameterized libraries contain traffic generators, statistics viewers, processing flows, resources, architecture components and application-specific functions. The outputs from VisualSim are a highly optimized design, executable specification and virtual platform to verify implementation.

The examples contained on the pages linked below demonstrates the model construction and trade-off possibilities in VisualSim. User can experience VisualSim by clicking on the model links. The leads to a new Browser page that instantiate a pre-built VisualSim model to display and execute within the Web Browser. The user can click on an icon in the graphical model to view the parameters. Click on "GO" button to start the simulation. Double-click on names (model parameters) in the model view, change the values and execute the simulations.

VisualSim Architect, the desktop application, was used to construct these models. Over 250 additional models are shipped with VisualSim. To experience model-based design using VisualSim, request for an Evaluation or send us an email.

Java Runtime Environment is reqired to view the Demonstrations, 

To download click here


Traffic Management for QOS by applying Backward Pressure:
Studies effectiveness of the RR algorithm for a various number of queues and evaluates QOS for backward pressure system.

Resilient Packet Rings
This evaluates the Ring occupancy and segment utilization for a implementation of the RPR.

SPI-3 Interface
This models the Physical-Layer to Link-Layer part of the SPI-3 for a 32-bit interface.

Route Optimization System
Explore the changes in the routing table when a link is dynamically a added or removed. The performance impact and the use of connectionless modeling methodology is described through this design.

TCP/IP Modeling
This model studies the impact of the packet retry rate on protocol buffering at different points on the network. The network is built with various nodes having different number of layers of the protocol stack implemented in detail (MAC, TCP and IP layers).

Verify Server Implementation on a Network System
The system optimized in the Dual Processor Architecture is introduced into the TCP Protocol Stack system as the implementation of one of the router nodes on the network. The traffic and hardware sizing are maintained similar to the previous case. The results show that there is difference in the performance graphs of the system when analyzed in isolation than when studied with the environment.

A/D Converter
Implements a Sigma-Delta A/D Converter with a second order sub-system.

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