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Mirabilis Design provides performance analysis and architecture exploration solution for the design of electronics and real-time software. The product, VisualSim, is a graphical modeling and simulation environment. Models of the proposed system are constructed by engineers in VisualSim using parameterized modeling library and C/C++/Java/SystemC/Verilog/VHDL. Designers and architects can conduct trade-off studies by varying parameter values, executing different input traffic stimulus and modifying the system configuration including the topology. The parameterized libraries contain traffic generators, statistics viewers, processing flows, resources, architecture components and application-specific functions. The outputs from VisualSim are a highly optimized design, executable specification and virtual platform to verify implementation.
The examples contained on the pages linked below demonstrates the model construction and trade-off possibilities in VisualSim. User can experience VisualSim by clicking on the model links. The leads to a new Browser page that instantiate a pre-built VisualSim model to display and execute within the Web Browser. The user can click on an icon in the graphical model to view the parameters. Click on "GO" button to start the simulation. Double-click on names (model parameters) in the model view, change the values and execute the simulations.
VisualSim Architect, the desktop application, was used to construct these models. Over 250 additional models are shipped with VisualSim. To experience model-based design using VisualSim, request for an Evaluation or send us an email.
Java
Runtime Environment is reqired to
view the Demonstrations,
To
download click here
 
Functional
Processor Model
This is the first level processor model. Processor is defined using queue as a pipeline, instruction set, simple execution unit, bus requests, latency,
queuing and contention. There are reusable blocks of bus port, arbiter and bridge.
Functional
Cache Model
Models a functionally and timing accurate L1 and L2 cache
architecture with a variety of standard parameters including
prefetch, pre-load, N-Way Associative, Replacement Policy, Lines,
Tags and Index. This model uses the ARM-1136J (F)S trace files
Crossbar
Switch Chipset
Architect a high bandwidth multiple
port IO System connected to a Switch
Cloud Chipset through a bridge.
Switch cloud is attached to multiple
of CPUs, Cache, DMA and others.
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