Performance Modeling of Cache Structure

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VisualSim can be utilized for analytical analysis in the same manner as it can be used for detailed architecture modeling. This models the L1, L2 and L3 caches. The processor generates instructions based on a given schedule. Using a cache-hit ratio for each stage, an evaluation is performed to compare utilization and response times for various rates of the cache-hit ratio.

This model differs from the Analytical cache model in that it includes additional parameters, more complex processor traffic variations, additional plotting options and includes a function on stall. The stall modulates the transmission through the system based on buffer occupancy downstream.

The model is created using a standard flow of data model. The traffic generator in the Processor generates traffic based on a uniform random distribution. The caches are all identical in model. The latency and queuing are modeled as a FCFS resource, a standard block in VisualSim. The hit-miss decision is based on a random distribution using the hit-ratio parameter value that is provided by the user.

This model uses 4 blocks (DS_Generate, DS_Select, DS_Insert and a Resource_Queue) to construct the whole model. For performance models there are 20 blocks that will be used over and over again. These are part of the Digital library.

The top-level of the model and the graphs are provided in this model.