Click
here to view the interactive VisualSim
Block Diagram and model
Modeling and Refining Architecture Resources at Transaction Levels
This VisualSim model covers the definition of architecture
details for optimization of the architecture and for mapping the behaviors
against these architecture resources.
The Bus has been modeled in message and timing accurate with a detailed
burst arbiter scheme. The cache has been
modeled as a function of a distribution with varying cache hit-ratio as a
function of the total memory loading.
The processor is defined with a set of instructions, speed, width and
pipelines.
Model Details:
The two traffic generators (Yellow blocks) are generating
parallel sequences of instructions that are being executed at the two
processors respectively. The topology of
the green blocks in the model forms the architecture under study. The traffic generators are used to stimulate
the model and generate activity. The top
processor receives a series of Write while the bottom processor receives Read
instructions. The Bus structure handles
the routing between the devices.
Simulation Analysis:
- Click
on GO to execute the simulation below.
- Next
modify the burst size to 1500 and execute the simulation. Notice the change in the Bus utilization
statistics and the Read/Write latency
- Now
modify one of the processor speeds to 70.0.
- Vary
any other parameter and notice the change in the performance. Some values will even demonstrate the
processor is not adequate to support the rate of arriving instructions.
