Click
here to view the interactive VisualSim
Block Diagram and model
Click
here to execute the VisualSim model
and view analysis results
The
system is a hardware platform that
can be utilized to execute a variety
of software applications. The model
constructed here studies the bus
utilization for a varying amount
MPEG traffic load. The rest of the
system from the MailBox and the
Application Processor Bus is abstracted
as a traffic model.
The
purpose of this experiment is demonstrate
the use of the Schedulers for exploring
hardware architectures and to describe
the data flow model.
System
Overview
The block diagram in Figure 1 shows
the platform architecture. The architecture
consists of the separate bus and
processor system interfaced using
a MailBox with associated memory.
The incoming frames are stored in
the Memory (MDP). Depending on the
type of data (Audio or Video), the
data is processed by DP1 or DP2.
The processors can make request
to their individual caches (CL1
and CL2) to retrieve the application
software. The two section work identical.
Figure 1: Block Diagram
of the Hardware Platform |
Model
Description:
Figure
2: Translation of the Dual
Processor portion of the
MPEG system
architecture
into VisualSim
The
data flow in ( Model 1 )is
described above.
|
Model
Notes:
