VisualSim Architect

VisualSim Architect is the graphical and hierarchical environment for model capture, interactive simulation execution and analysis. Using the libraries and custom-coded blocks, the users can assemble complex systems in a very short period of time. The organization of VisualSim and the interface to libraries is shown in Figure 1.

VisualSim is a full functionality package for Model-Based Design, Transaction Level Modeling, Cycle-Accurate modeling and design verification. Designers and architects can conduct trade-off studies by varying parameter values, executing different input traffic stimulus and modifying the system configuration including the topology. The outputs from VisualSim are a highly optimized design, executable specification and virtual platform to verify implementation. VisualSim contains a highly optimized simulation engine that is fully compatible with the OSCI SystemC kernel.

Figure 1: VisualSim Architect- Performance and Power Modeling

Models of the proposed system are constructed by engineers in VisualSim using parameterized modeling library and C/C++/Java/SystemC/Verilog/VHDL. The parameterized libraries contains blocks that emulate traffic generators, statistics viewers, processing flows, resources, architecture components and application-specific functions. Each block has a unique set of parameters that are modified to create the required functionality. Probes can be setup anywhere in the model graphically to automatically generate pre-built and custom statistics.

Optimizations are performed by running simulations by performing a parameter sweep. The results can be interactive or saved to desktop for future post processing.

• Model Development Environment
Graphical Block Diagram and Finite State Machine Editor
Hierarchical model construction
Embedded block documentation
Built-in debuggers peek into the operation of the block and ports
Illustrative diagnostic messages eliminate model construction errors
Model animation for visual presentation
• Simulators
Untimed Digital
Timed: Event-Triggered, Cycle-Accurate and Cycle-Approximate
SystemC
Continuous Time
Graphical Finite State Machine
• Modeling IP and Libraries
Traffic Generators
Statistics Generators
Performance Resources
Mathematical and transformation
Application-specific- Wireless, DSP, Imaging, Analog, Control Systems
Scripting- C-like Scripting with a huge API of modeling functions, Python and Tcl
• Database
XML with user-extendable DTD
• Interfaces
Wizard- Import outside IP without using custom transactors and wrappers
Hardware- Verilog, VHDL, Hardware-in-the-loop and Serial I/O
System- Files, Excel and STK
Middleware- CORBA, RMI and Datagrams

Key Benefits