VisualSim
SystemC modeler provides a graphical environment for users to capture
their system using a combination of pre-built modeling libraries (TLM)
and custom SystemC modules. The environment is supported on
Windows and Linux. The environment has a extensive library to
jumpstart your model construction. Based on customer experience,
the time saving can be up to 2 man-years on a major project.
VisualSim supports TLM 2.0 in the latest release.
Some of the libraries include:
- Sources: Distributions, trace files, sequence and clocks
- Reports: Performance
(latency, utilization and throughput), power (instant, average and
cumulative), wareforms and multimedia (audio, image and movie).
- Compilers: Visual Studio, Gcc and Borland
- Debugger: Open link to interface with any debugger
- Animation and graphical viewers
- Performance modeling (TLM 3 and 2): Channels, pipelines, queues, schedulers and other shared resources
- Architecture models: Processors, caches, memories, buses, switches, DMA and controllers
- Open integration to system tools: C-code, MatLab, Excel and RTL simulators
- Power exploration and analysis
- Platform support- Windows and Unix
VisualSim
SystemC Modeler is a graphical model construction, analysis and
documentation environment. Standalone SC_Modules can be integrated as a
graphical entity for distribution or integrating with pre-built
modules. SC_Modules can be managed hierarchically and saved in
local libraries for easy access.
The environment provides for easy separation between SC_Modules and
also has a generic transaction payload. This allows for easy plug
n' play of standard and custom SystemC modules. Model development
can be reduced month.
For example, a user of the SystemC Modeler was able
to assemble a 3G smartphone wireless SoC model at Transaction and cycle-accurate detail in about 3 weeks.
In 3 additional weeks, the model was tuned, validated and analyzed. Within about 7 weeks, the entire project was
completed and proposals for modying the architecture and compensating it with software routines was designed.
A similar project using SystemC could take over 2.5 years to get done. The advantages were the pre-built modeling libraries,
the statistics generators and the debugging environment. Another group was able to take the same model and adapt it for a
multimedia application. Thus the same model could be reused by the rest of the company.
VisualSim SystemC Modeler addresses the challenges
inhibiting SystemC proliferation i.e. extremely long model construction time and the need for a C++ software expert.
Figure 1: VisualSim SystemC Block Parameters
OSCI SystemC standard and reference simulator define a language and
not a solution. SystemC provides the ability to interoperate with IP,
maintain compatibility between compilers, standard port and method
definitions, standard templates and the notion of thread. To be truly
efficient in SystemC, users must be proficient in complex C/C++
constructs such as constructors, methods, threads, pointers and
template libraries. Trivial simulation tasks typically have to be
constructed entirely with new C++ code development, a daunting task for
most hardware engineers and Architects. The build-from-scratch
SystemC approach can be extremely time consuming, and cause system
analysis schedules to exceed the allocated project deadlines. Current
solutions in the market from companies such as CoWare, Mentor Graphics
and Cadence are focused on code-level debugging and integrating
existing IP components. These are good for integrating models of
commercial IP, but not for building models of differentiated tchnology.
Using VisualSim SystemC Modeler, the user creates SystemC modules
for only the core and custom technology. Environmental models of
networks and channels, traffic generators, standard queuing structures
and analysis reports can be instantiated from the library on to the
graphical environment. The user conducts model-level debugging using
graphical listeners, animated executions and system-level assertions.
In SystemC Modeler, users can create new SystemC modules and execute
existing SC_Modules imported from other sources. To eliminate the
coding of mundane and repetitive tasks, the SystemC Modeler generates a
template with pre-entered information for ports, constructors and other
header information. The graphical environment can enforce a strict
modeling guidelines; maintain module connectivity graphically and in
XML; and vary SC_Module operations using graphical parameters. The
block diagram shown in Figure 1 illustrates a multi-stage pipeline
design using SystemC in VisualSim.
What is SystemC
SystemC
provides hardware-oriented constructs within the context of C++ as a
class library implemented in standard C++. Its use spans design and
verification from concept to implementation in hardware and software.
SystemC provides an interoperable modeling platform which enables the
development and exchange of very fast system-level C++ models. It also
provides a stable platform for development of system-level tools. The
Open SystemC Initiative (OSCI) is an independent not-for-profit
organization composed of a broad range of companies, universities and
individuals dedicated to supporting and advancing SystemC as an open
source standard for system-level design.
No longer to be thought of as an HDL replacement, SystemC
rather is the bridge that spans the chasm between the "whatif" work
done by system architects at the behavioral level with the
nuts-and-bolts, nitty-gritty "how" implementation work of the RTL
coder. Thanks to a new emphasis on transaction-level modeling (TLM),
SystemC bridges those worlds while facilitating hardware/software
co-simulation.
Until a few years ago, RTL was sufficient to enable designers
to manage the complexity of IC design. But the sheer complexity of
today's SoCs, coupled with a rise in IP reuse, has made an upward move
in abstraction a necessity rather than a luxury. SystemC gives
designers a vehicle for architectural exploration, but it's more than
that. It gives users a means with which to capture their design and
validate it running system software at a speed that provides useful
results.There's also the ability to use the same testbench that was
created at the system level down at RTL, so the effort in creating that
initial testbench is not wasted.
Current usage
The number one reason for the use
of SystemC is the significantly increased simulation performance at the
TLM level over executable platforms modeled at the RT level using
Verilog or VHDL. SystemC TL models are fast enough to serve as a
software development platform allowing for early software development
and for co-simulation of hardware and software. Both TL and functional
models are fast enough for system level architectural modeling and
analysis. The second reason for SystemC use is functional verification.
The same executable platform that is used to develop the software is
often used for verification of the entire system. This verification
occurs early on in a project and the TLM becomes a golden reference for
the entire system. Because SystemC is C++, it has a number of inherent
properties, such as classes, templates and inheritance, that lend
themselves to verification. These capabilities are extended with the
SystemC Verification Library (discussed later) making SystemC a
powerful verification language as well as modeling language.
