VisualSim- Bus Switch and Controller Modeling Toolkit

Generators

1. Shared and Linear Bus
2. Request Acknowledge Bus Controller
3. Point-to-Point Bus Controller
4. Ring Bus Controller
5. DMA Controller
6. Memory Controller
7. I_O Controller
8. Bridge
9. Non-blocking switch 
10. Blocking switch

Key Analysis and Features

• Define platforms for the purpose of optimizing the cost/performance/power, selecting the right devices and sizing the components.
• Explore bus topologies and protocols
• Large list of Bus standard available
• Models are setup to be cycle-accurate and functionally (message) accurate
• Custom arbitration or controllers described using VisualSim Library, Script, SystemC or C/C++ code.

Key Parameters

• Bus speed in MHz
• Burst Mode and size (burst, Word or Byte mode)
• Arbitration: First Come-First Serve (FCFS), FCFS with preemption and Custom
• Word width
• Number of memory banks, channels, drives and I/O devices
• Number of channels
• Fragment sizes
• Power states and levels- active, idle and custom

Statistics

Performance:

• Utilization
• Throughput
• I/O per Channel
• Latency
• Queue Occupancy
• Transactions rejected
• Number of transitions

Power:

• Instantaneous and cumulative power consumed by each device

All above reports record Mean, Minimum, Maximum and Standard Deviation.

Figure 1: Using VisualSim Bus, Switch and Controller Toolkit

Overview

As designs migrate to a platform-based approach, the unique differentiators are the custom IP and innovative topology. The VisualSim Bus, Switch and Controller Modeling Toolkit enables designers to construct models of custom on-chip and in-system buses, DMA, memory controllers and other hardware controllers. The modeling toolkit has the required infrastructure to create complex topologies, handle connectivity, functional messaging, priority, preemption and standard statistics such as IO's per second, utilization and buffer occupancy. The user can customize the arbiter or define leading-edge protocol of the connectivity at a cycle- and transaction-accurate detail.

Using this modeling toolkit, designers can create system models of their designs and quickly explore new architecture concepts based on performance, functionality and power. The architect can explore the impact on performance and power for difference combinations of I/Os and memory configurations. This library can be used in conjunction with the VisualSim Architecture Library or other Instruction Set Simulators to simulate a complete system. The VisualSim modeling libraries provide the traffic generators and can be used to construct the details of the protocol logic to work with this modeling toolkits infrastructure blocks.

Designers can accelerate the construction of virtual prototypes of current and next generation buses, switches and controllers. The library is expected to reduce the development time of a PCI-Express or AXI bus from about 4 weeks to less than 1 week. This library enables users to easily mix-and-match bus descriptions at different levels of abstraction without modifying the rest of the system. The models of these custom components can be at over 95% accurate for functionality and performance; and over 85% for power consumption.

Use Model

The Bus Library is designed to be cycle- and message- accurate and extendable using library blocks, scripting language and C code. Multiple instances of this library can be used in a single model. Bus configuration and their status can be modeled as external transaction traffic. Users can integrate the Bus Model with the Architecture library components such as processors, or use standalone in a model. The Bus Model has a built-in Routing table that is updated with the connectivity that initialize with a hello message. Processor model generates the connectivity hello messages automatically. In a standalone bus, user can enter the routing information in a table.