VisualSim Bus and Network Standard Simulation Models

SoC AMBA 2.0: AHB and APB AMBA 3.0: AXI CoreConnect: PLB and OPB Interconnect PCI-AMBA Interface	Board-Level VME- Parallel & Daisy ( Details) PCI and PCI-X PCI-Express SPI 3.0 (Details) USB Rapid IO
Industrial Networking 1553B FlexRay (Details) CAN	Networking Switched Ethernet Resilient Packet Ring (Details) RP3 Wireless LAN 802.11 a/b/g (Details) Bluetooth (Details) Sensor Networks (Details)

This library extends the Bus, Switch and Controller library by providing validated models of  industry-standard bus and networking technologies. The controller algorithm, arbiters and timing control are built to the specification standard. These libraries are built using VisualSim modeling libraries and Script. These bus components can be combined with other standard and custom architectural components such as processors, memory and RTOS to form the full system.

The model are defined at Burst Transaction Accurate level. Each Bus component will meet the timing diagram for the request, acknowledge, fragment, read and writes. These buses will operate at cycle-accurate and behavior-accurate. The functional messaging and protocol behavior relevant to capture performance and power consumption of the data and control transfers are included. Model accuracy has been validated against standard traffic traces and timing diagrams available from the standards committees. The actual data can be optionally transfered, as well. The Bus transactions, Data-Link, MAC and configuration for end-to-end devices are modeled to achieve the above accuracy.