Verilog/ VHDL Interface

VisualSim provides a VPI/PLI-based interface that can be used to co-simulate with any standards-compliant Verilog simulator. VHDL users can use the SystemC or the C interface to communicate with VisualSim. A custom FLI interface to ModelSim VHDL is available on request. The interface generates all the required files for the co-simulation. This interface is used to validate implemented blocks and for reuse IP that is already available.

The interface is part of the System verification methodology provided VisualSim. The system model is the Golden Reference. The Verilog or VHDL code must be validated against this reference. The same stimulus that triggers the VisualSim model triggers the Verilog code. The output of the RTL is compared with the VisualSim, adjusting for some minor variations in clock cycles. The validation can be done at a module or full chip level.

The VisualSim interface to Verilog and VHDL has been tested with a number of simulators. All the data types of the standard can be used for the automatic interface code generation. The name of the Verilog/VHDL files is specified and then the Verilog data types for the input and output are entered.

The interface is currently supported only on Linux and Windows platforms.