VisualSim-- Xilinx FPGA Modeling Toolkit

VisualSim Xilinx FPGA Modeling Toolkit provides a rapid prototyping and architecture optimization platform for Xilinx Virtex based products. This is a graphical prototyping environment that contains standard hard IP available from Xilinx for the Virtex 4 and 5. Using these pre-built library components, the user can quickly assemble a representative model of the proposed hardware architecture. Adding the traffic and software task generators, the full system can be simulated to compute the performance metrics. Combining these FPGA models with other pre-defined modeling IP blocks, users can construct model of their full systems such as a router, security appliance, industrial and automotive platforms, and other multimedia devices. Within VisualSim Architect, designers can select the right architecture by conducting rapid and extensive performance trade-offs during the product definition phase.

VisualSim Xilinx FPGA Modeling Toolkit enables designers of high-performance applications using FPGA to explore performance bottlenecks. Unlike verilog/VHDL and schematic solutions that require detailed knowledge of the device, the VisualSim models can contain pre-configured components with pre-built models. These models are at a are transaction-level and can be customzied by the user with minimal effort. The model of a large and complex can be constructed in a matter of a few days.

Xilinx ESL Initiative

Click here to visit the Mirabilis Design ESL Page at Xilinx. This Xilinx FPGA Toolkit has been built in partnership with Xilinx and is targeted at developers of high-performance, high-availability products that use Xilinx FPGA products. Mirabilis Design is a member of the Xilinx ESL Initiative. The Xilinx partnership will provide FPGA and System designers a significant architecture exploration solution that increases confidence in the architecture and eliminate design bottlenecks.

Product

The product is built on top of the industry-standard VisualSim Architect. The FPGA Toolkit can be used in conjunction with the application-specific, processing functions, resource and architecture elements available in VisualSim. The modeling components provided in the FPGA library have been configured to represent the IP, cores and Fabric resources. This includes the parameters, list of standard statistics output and possible connectivity options. A list of the important toolkit components are:

1. Platforms (Virtex 4 and 5 Family)
2. Processors/Cores (PowerPC and MicroBlaze)
3. Bus and Controllers (CoreConnect- PLB and OPB, Fast Simplex Link Bus, DDR and DMA)
4. Memory (SDRAM, SRAM, Block RAM and Cache)
5. Communication Devices (Ethernet, PCI and PCI-Express)

Architecture Optimization

The FPGA Modeling Toolkit is used early in the design cycle to

• Validate the architecture assumptions to meet the requirements
• Determine the performance and power consumption
• Identify bottlenecks
• Generate the product specification and verification test suite
• Evaluate the functionality and operation of the FPGA architecture in the full system

Overview

The Xilinx FPGA Modeling Toolkit provides modeling blocks that emulate the standard FPGA Platforms and IP/Cores. These include processors, DMA, memory, buses and controllers. Using these components, a designer can capture a model of the proposed architecture using the Xilinx Virtex platforms. The model can at the FPGA-level of a system containing one or more FPGAs. The model can contain the details of both the hardware and software architecture.

This library has been built to enable designers to quickly put a prototype of their proposed system and simulate with various combinations of applications and traffic profiles. This environment is used prior to the availability of important information such as the application software, pin-level or bit-level connectivity, input traffic streams and operating environments. Other VisualSim modeling toolkits provide the modeling components required to quickly describe a set of target application, application-specific traffic sequence and associated user-activity. The built-in statistics generators can be tuned using graphical parameters to specify the expected output analysis. Using this environment, user can trade-off lowest cost; highest target performance; maximum availability; minimal power consumption; and right functionality.

Design Exploration

Using the Xilinx FPGA Modeling Toolkit, VisualSim Architect can be used to study a variety of architecture trade-off including:

System

• Optimal distribution of application, control and protocols between board-level components and FPGA
• Select the right FPGA platform and combination of IP/Cores for the target application
• Migrating external Processor to on-chip PowerPC

Hardware

• Partitioning the application or protocol between the PowerPC, MicroBlaze and Fabric
• Sizing processors, memory, buses and other active resources on- and off- the FPGA
• Determine the utilization and effective throughput across the CoreConnect (PLB and OPB), FSL Bus, DMA and memory controllers
• Allocate Block RAMs to operational task for low-latency and minimal DMA overhead
• Effects of redundancy and radiation hardening on system availability

Software

• Offloading processes on to Co-Processors using the APC or a separate dedicated FPGA
• Load balancing software tasks onto multiple PowerPC or MicroBlaze
• Performance and stalling effects of parallel and concurrent software operation
• Test for functional and software flow correctness

Benefits

VisualSim FPGA Toolkit can identify design bottlenecks, gain greater coverage of the exploration over spreadsheets and validate your architecture prior to implementation. Using VisualSim means that Architects and Designers do not have to make simplistic assumptions using spreadsheets or spend a lot of time developing detailed C models. They can get the detailed results and accuracy of a cycle-accurate and message accurate C-model using a model that can be controlled using a spreadsheet. Architecture exploration, prior to implementation, will guarantee that your design will work the first, meet the customer requirements and can be manufactured without significant problems. All of these ensure that you have the highest quality product, at the optimal price, required performance and lowest possible power consumption.

Use Model

The Xilinx FPGA Toolkit is intended to be used by engineers that need to implement complex protocols, processing intensive application and controllers on FPGAs. The simulation can study how the FPGA will perform when different application sequence or user-input is provided. Also, the interaction between multiple FPGAs, ASIC-FPGA, and system components and FPGA can be studied. This Toolkit can be used throughput the product development process. Major design phases include early hardware and software architecture design phase; changes made to the architecture due to the requirements changing; implementation verification; and product testing.

Statistics and Analysis

The library has a number of standard statistics that are generated at the end of each simulation run. The user can customize the list of analysis that will be output for each simulation. The results can be for both the FPGA and the system that the FPGA is operating within.

Processor Performance:

Pipeline stalls

Context switching time

Hit-Ratio for the cache, RAM and external SDRAM

Idle time

Timing diagram showing application activity

Performance:

Utilization

Throughput

I/O per Channel

Latency

Queue Occupancy

Transactions rejected

Number of transitions

Power:

Instantaneous and cumulative power consumed by the full system and the individual devices

For each of the above statistics, the Mean, Minimum, Maximum and Standard Deviation are recorded.