VisualSim can provide detailed visibility into the performance, power, functionality and
logical correctness of your proposed or derivative design.
VisualSim is used in the design of large system, boards, real-time software, SoC,
custom ICs, processors and FPGAs. VisualSim models are constructed using
the extensive library of modeling components. For more details on modeling
libraries, visit the Products section. There are over
2000 analyses and probes available to capture instantaneous and consolidated statistics.
Every resource and architecture library element generates a unique set of statistics
specific to the functionality in that block.
All models are constructed using the
library components. Advanced components such as processors and bus protocols are
defined using the architecture library. A custom
processor or co-processor could be constructed using a combination of the basic
modeling library, processor generator and the scripting language. A
proprietary bus protocol could be constructed using the resources and processing
blocks to execute at functional level and 100% timing accuracy.
There are
four levels of abstraction in the system design flow prior to scheduling implementation.
Performance or Queuing Model: This is commonly known as traffic
engineering or abstract Transaction-Level modeling. These are statistical models based
on Markoff processes. Models of processors, switches and networking devices are
initially constructed at this abstraction to gauge the overall performance. These
models would define the incoming traffic using emperical distributions, processing
resources as timed queues and shared elements as virtual named resources.
The input traffic distribution and timing; packet attributes such as size, priority and
overhead; and resource sizes such as FIFO depth and bus speed will be varied to gain maximum coverage.
Statistical models can also be used to optimize power scheduling, protocols, chip
routing techniques and traffic management schedulers.
Hardware Sub-System Design: A special case of the architecture exploration is a hardware sub-system. Common examples of this modeling are bus, switch and processor design. This modeling is used to evaluate the protocol, size the queues and optimize the protocol parameters. This modeling is used on both standard and custom protocols. The exploration is important for the standard protocols to maximize the performance with the protocol limitations.
These models are constructed as flows of hardware sequences. There are a variety of Req/Ack, Read and Write options. In this case, the focus is on the sequence of instructions and the consumption of resources. Resources can be DMA channels, queues and execution units. Unlike the system architecture exploration, these models combine the behavior and architecture into a single low. The behavior flows are the constraint-driven flow across the hardware sub-system units.
Platform Design- Semiconductor/FPGA/System: These utilize timed,
cycle-approximate and cycle-accurate modeling. Platform models are created using
the separation of behavior to architecture mapping methodology available in
VisualSim. A mobile multimedia SoC model could contain multiple ARM/PowerPC processors, MPEG co-processor, RAM, ROM,
SDRAM, Flash, multiple AHB, custom hardware acceleration and MPEG scenarios.
An Xilinx FPGA model of a Layer 3 switch implementation would contain a
PowerPC core, Ethernet, FSL, Core-Connect, SDRAM and multiple MicroBlaze.
A system model for a 3G Data Router with ATM internal processing would consist of multiple boards,
IC, SoC, processors and FPGA. The system model would have great emphasis on the bus
interaction while the semiconductor/FPGA model focuses on the
internal processing of a component or IP block. The
use-cases and scenario executing on this platform will be described as flowcharts.
Using the dynamic scheduling technology, various mapping schemes
can be experimented with. These types of platform models are used to conduct
hardware-software partitioning, power reducting schemes, bottleneck identification and device selection.
Multi-Domain Design: This type of modeling is typically a untimed transaction model. A Wireless
system must model the RF/analog front-end,
Physical layer DSP, protocols, imaging algorithms,
network environment and overhead traffic.
Combining the VisualSim multi-domain
simulation and extensive libraries, all of
the above engineering domains can be included
in a single model with each domain operating
in it's exclusive time dimension. The Analog can be modeled in
the continuous-time with the Analog library;
DSP and imaging in Untimed Digital with
their respective libraries; Protocols using
Finite State Machine; and
the network environment and overhead traffic
using
Digital simulator and the Processing
library.
