Block Name: PCIe6_Bus
Library location: Interfaces and Buses -> PCI -> PCIe6_Bus
Code file location: $VS/VisualSim/actor/arch/Buses/PCIe6_Bus

Table of Contents
1. Block Overview
2. Description
3. Key features
4. Example Models
5. Configuration
    5.1 Required input Data Structure Field
    5.2 Blocks which can be connected to the PCIe6_Bus
    5.3 Sample Test case Scenarios
6. Block Ports
7. Parameters

    1. Block Overview

  This library emulates all the functionality of the PCIe6_Bus standard. There are a total of 12 device/network interface ports for this block. For this block to operate correctly, the model must contain two blocks as a prerequisite- Architecture_Setup, and Digital Simulator. To satisfy the market demand for a high-speed, low-latency interconnect, the PCIe6.0 features improves the bandwidth and power efficiency.

    2. Description

PCI Express (PCIe) provides a scalable, high-speed, serial I/O bus that maintains backward compatibility with PCI applications and drivers. The PCI Express layered architecture supports existing PCI applications and drivers by maintaining compatibility with the existing PCI model. PCI Express having parallel bus topology and Multiple point-to-point connections. A switch may provide peer-to-peer communication between different endpoints and this traffic. A PCI Express link consists of dual simplex channels, each implemented as a transmit pair and a receive pair for simultaneous transmission in each direction. Each pair consists of two low-voltage, differentially driven pairs of signals.


 PCIe6_BUS Block Diagram:
PCIe6_Bus Block Diagram


3. Key features
    1. The PCI Express library comprehends future performance enhancements via speed upgrades and advanced encoding techniques.
    2. Generation of Bus statistics. Throughput in Mbps, Bus utilization in percentage, Input/Output transactions /sec, Root complex buffer occupancy and End point buffer occupancy values
    3. Block debug feature, this enables the user to visualize the active transaction, current time and channel.
    4. User can apply flow control for root complex and end point
    5. PAM4 Signalling
    6. Forward Error Correction(FEC)
    7. FLIT Mode
    8. L0P Mode

    4. Example model list

        1. PCIe6_Device Interface2x2_base_model.xml
        2. PCIe6_Device_Interface3x3_model.xml
        3. PCIe6_Device Interface_6x6_model.xml
        4. AMBA_AXI_PCIe6_Interface.xml
        5. AMBA_AHB_PCIe6_model.xml
        6. AMBA_AXI_PCIe6_AMBA_AHB_model.xml
        7. ABHA_AXI_2_PCIe6__AMBA_AHB_2_model.xml
        8. Switch_PCIe6_Interface_model.xml
        9. PCIe6_Device Interface_parameter_testing_model.xml
        10. PCIe6_AMBA_AXI_Parameter_Model.xml
        11. PCIe6_Transaction_base_script_model.xml

    5. Configuration
   
    To include the PCIe block in a model, the following steps must be followed:
      5.1 Required input Data Structure Field

    Use the Data Structure template defined by the name "Processor_DS". Along with the fields defined with in "Processor_DS",  add the following:
   

Data Structure Field Description Value (Examples)
A_Source Source or Root Complex device name Source
A_Destination Destination or End Point device name Destination
A_Hop Transaction flow path towards destination A_Destination
A_Command “Read” or “Write” operation Write or Read operation
A_Bytes    Number of data Bytes for this transaction 1024
   

      5.2 Blocks which can be connected to the PCIe6_Bus       
       5.3 Sample Testcase Scenarios       
        Model: 2Masters and 2 Slave Model
        The communication process happened through 2 Pins input (Left side) , 2 Pins output (Right side) of PCIe 6 Switch model
        Case1:
        Destination: DRAM1, Write operation, 512 Bytes
        Destination: DRAM2, Write operation, 512 Bytes
        Case2:
        Destination: DRAM1, Write operation, 1024 Bytes
        Destination: DRAM2, Write operation, 1024  Bytes
    12 input/output ports + 1 debug port
    7. Parameters
Parameter Explanation  Example 
Architecture_Name “Architecture_1” (String) Name of the Architecture_Setup block
PCIe_Switch_Name “PCIe6_Switch” (String) Unique name for this Bus. Different from all architecture blocks and global model memories.
Max_Read_Req_Size_Bytes 4096 (int) (bytes) This is the max Request size for a packet that can be recieved at any Endpoint ports of the switch.
 If it is greater than the value specified here, then an error is thrown.
Flit_Size_Bytes 256 (int) Flit_Size is the fixed size in Bytes which is used to define the packet size when sending the packet from sender to receiver ports. 
Number of Lanes 16(int) 1,2,4,16,32, and 64 are the only possible values.  The user is restricted to these values only.
This can be a single value or an array of the Number of Master.

Buffer_Size_Bytes {4096,4096} //RX,TX Number of Bytes irrespective of the number of transactions for Rx and Tx. 
Overhead_Cycles 0 (int) For Each frame - EndPoint Rx Buffer to Crossbar and Crossbar to EndPoint Tx Buffer, Overhead_Cycles will be added to the total delay cycles.
Devices_Attached_to_Ports {{"Dev_1"},{"Dev_2"},{"Dev_3"},{"Dev_4"},{"Dev_5"},{"Dev_6"},
{"Dev_7"},{"Dev_8"},{"Dev_9"},{"Dev_10"},{"Dev_11"},{"Dev_12"}}
This is a 2-D array which the user can use to specify the device names of the devices attached to each EndPoint. It the connected Device has the capability to send the Hello Message, then user shouldnt worry about updating this array as it will be updated automatically once it receives the hello message.
Enable_Debug true (boolean) Set it to true and connect a TextDisplay to the Debug_Port (south side of the Switch) to view all the sequences happening within the PCIe_Switch.
BER 1.0E-11 (double) Range is 0.0 to 1.0.  During CRC check, a random number is generated.  If the number is below this BER, a Nack is returned.  If above, the transaction is accepted.
NumberOfRetry
4 (int)
If the transfer gets failed due to CRC Check sum failure, then it would be retransmitted. But if the same frame gets failed continuously, then it cannot go above the NumOfRetry value. If it goes above the NumOfRetry value, then the transaction is dropped at the PCIe6_Switch.
Timeout 6E-6 (double) Timeout specifies the amount of time to wait for an acknowledegment to arrive for a FLIT that was transmitted prior. If the Ack is not received within the Timeout expires, then the corresponding FLIT is retransmitted.
Enable_Master_Flow_Control false (boolean) Set this parameter to be true if Flow Control needs to be enabled between the transaction initiator and the PCIe6_Bus. Setting this parameter would mean that All EndPoints are now operating under the effect of Flow Control (Meaning that the incoming Data Structure must contain "Event_Name" field). User can add a field called "Master_Flow_Control_Enable" and set it to be false if the connected EndPoint doesnt wish to have Flow Control Enabled.
Enable_Slave_Flow_Control false (boolean) Set this parameter to be true if Flow Control needs to be enabled between the PCIe6_Bus and Destination EndPoint. Setting this parameter would mean that All EndPoints are now operating under the effect of Flow Control (Meaning that the PCIe6_Bus would wait for the Event to be generated so that it can send the next packet out to the connected EndPoint). User can add a field called "Slave_Flow_Control_Enable" and set it to be false if the destination EndPoint doesnt support Flow Control.
Replay_Buffer_Size_Bytes 1024
Store a copy of all Transmitted TLPs until the remote receiver acknowledges them.
Number_Of_Successive_Acks 3 Number of Successive Acks used by Selective naks provided Selective Aak is supported. PCIe6 supports Selective Nak on top of classical Nak. With Selective Nak, just a selective FLIT can alone be retransmitted there by saving bandwidth. For this to happen,  "n" number of consecutive Naks should be received at the sender . Then the sender identifies it as a retransmission request  and retransmits the FLIT. ("n" is the value set for this parameter). For Classical Nak, it  request for a group of FLITS  to be retransmitted. Often happens when FLITS are received in out of order  or a FLIT in between found to be missing etc..
Enable_Selective_Ack true Setting value true would enable Selective Ack feature on top of Classical Ack.With Selective Nak, just a selective FLIT can alone be retransmitted there by saving bandwidth. For this to happen,  "n" number of consecutive Naks should be received at the sender . Then the sender identifies it as a retransmission request  and retransmits the FLIT. ("n" is the value set by Number_Of_Successive_Acks). For Classical Nak, it  request for a group of FLITS  to be retransmitted. Often happens when FLITS are received in out of order  or a FLIT in between found to be missing etc..
Enable_Hello_Msg_Forwarding true In VisualSim, All connected devices send a message called "Hello_Message" at startup. This is to make sure that the Buses, interconnects, bridges know where each of the devices are located. Enable this parameter to forward the hello message received on one port to all other ports. In a big network, enabling it would be helpful (provided there are no bus connections in loop).