Modem_V6

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Modem_V6model <h2>TMS320DM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Bus_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>TMS320DM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>NAND_Flash_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>Hierarchical_Block</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Comm_Delay</td><td>10.0e-3</td><td>0.01</td></tr></table> <h2>ADC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>DAC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Ethernet Interface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>12800.0</td><td>12800.0</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Data_Rate</td><td>{20,100} /* {Min Mbps, Max Mbps} */</td><td>{20, 100}</td></tr><tr><td>Data_Size</td><td>{40,400} /*{Min Bytes, Max Bytes} */</td><td>{40, 400}</td></tr></table> <h2>TI DSP</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Processor_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr><tr><td>Bus_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr><tr><td>NAND_Flash_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>M&C and Waveform Selection</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>FPGA_Clock_Speed</td><td>FPGA_Clock_Speed</td><td>200.0</td></tr></table> <h2>DeModulator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Modulation_Factor</td><td>&quot;8PSK&quot; /* &quot;QPSK&quot;, &quot;8PSK&quot;, &quot;16QAM&quot;, &quot;64QAM&quot;*/</td><td>&quot;8PSK&quot;</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>FEC Decoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Alignment_Dly</td><td>6 /*cycles */</td><td>6</td></tr><tr><td>Transcoding_Mapping_Dly</td><td>2 /*clock cycles*/</td><td>2</td></tr><tr><td>Parity_Generation</td><td>2 /*Cycles*/</td><td>2</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Differential Decoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Dly_Cycles</td><td>2</td><td>2</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Descrambler</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Dly_Cycles</td><td>10</td><td>10</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Data De-Framer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Modulator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Modulation mapping based on Symbol (BPSK, 4-PSK, 8-PSK, 16-QAM, 64-QAM, 128-QAM))</td><td>Modulation mapping based on Symbol (BPSK, 4-PSK, 8-PSK, 16-QAM, 64-QAM, 128-QAM))</td></tr><tr><td>Modulation_Factor</td><td>&quot;8PSK&quot; /* &quot;QPSK&quot;, &quot;8PSK&quot;, &quot;16QAM&quot;, &quot;64QAM&quot;*/</td><td>&quot;8PSK&quot;</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>FEC Encoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Should perform based on INTELSAT FEC rates</td><td>Should perform based on INTELSAT FEC rates</td></tr><tr><td>Alignment_Dly</td><td>6 /*cycles */</td><td>6</td></tr><tr><td>Transcoding_Mapping_Dly</td><td>4 /*clock cycles*/</td><td>4</td></tr><tr><td>Parity_Generation</td><td>2 /*Cycles*/</td><td>2</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Differential Encoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>I bit delay and XOR Operation</td><td>I bit delay and XOR Operation</td></tr><tr><td>Dly_Cycles</td><td>2</td><td>2</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Scrambler</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Scrambler will randomize the data stream that needs to be transmitted.</td><td>Scrambler will randomize the data stream that needs to be transmitted.</td></tr><tr><td>Dly_Cycles</td><td>10</td><td>10</td></tr><tr><td>Clock_Speed</td><td>200.0</td><td>200.0</td></tr></table> <h2>Data Framer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Data Framer Receives IP data through Ethernet Interface. \\nIn this model the size of data received is 100 Mb. DataFramer \\nwill fragment the data into 25 bits (Need to check). Full Frame will\\nwill be sent out for every 125 useconds total of 12500 bits\\n </td><td>Data Framer Receives IP data through Ethernet Interface. \\nIn this model the size of data received is 100 Mb. DataFramer \\nwill fragment the data into 25 bits (Need to check). Full Frame will\\nwill be sent out for every 125 useconds total of 12500 bits\\n </td></tr><tr><td>Overhead_Rate</td><td>125.0e-6</td><td>1.25E-4</td></tr></table>