Partitioning Hardware-Software Functionality between Architecture Resource

 

This VisualSim model provides an introduction to partitioning of functionality within a mobile phone.  Every system has a number of use-cases that are triggered by a request for service or by arrival of data.  The data can be from an antenna, interface card or connected bus.  Each source of data has to go through certain processing steps before it sent on an output port, displayed on the LCD or sent to a speaker.

 

This model consists of 4 input sources- 2 Video streams, one speech and one WiMax high-speed data input.  Each source data has to go through a number of processing steps.  The processing steps for the Video Frame have alone been defined in this demo.  More details and specific implementation can be added by the user.

 

The top-level model and the associated simulation analysis are shown below in the VisualSim Executable models.

 

The output from each of the traffic sources flows through every block in the flow.  Each block has a functional described within the block.  The behavior is the actual task performed on the incoming data.

 

There are 5 architecture resources in this model- RTOS, memory, DSP, Up and ASIC.  Every behavior is first sent to the RTOS.  The RTOS stores a copy of the data in the memory and then assigns the instruction to be processed on either the ASIC, uP or DSP depending on pre-specified assignment.

 

Each behavior block can be executed on either the uP, ASIC or DSP architecture resources.  Executing it on each of the resources requires different quantity of the resource being used.  For example, the Stabilize may require only 6 cycles on the ASIC while it may require 14 on the uP.  The same process will consume different quantity of power on the uP vs. the ASIC.  Also there is a cost difference between the two resources.

 

So, the selection of the partitioning is based on the total power consumed, the performance and the cost. 

 

Simulation Analysis:

The user can vary the parameter on any of the blocks in the model.

  1. Vary the Speed_Mhz of the uP, DSP or ASIC and notice the change in the Resource usage plot.
  2. Modify the active and standby power for the DSP, ASIC, uP or Memory Resource to see the change in the power plot
  3. Modify the Destination_Processor parameter in the behavior blocks and see the change in the Resource_Usage plot.

 

All the Hierarchical levels are shown in associated windows:

View of the VisualSim model of a Video Frame Traffic Source

View of the VisualSim model of the RTOS

View of the VisualSim model of the Memory

View of the VisualSim model of the uP

View of the VisualSim model of the Stabilize behavior block in the Video Frame flow

 



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