VisualSim Technology IP

Library of stochastic, scripting, hardware, software, traffic, RTOS, schedulers and interfaces

A library of over 150 Technology IP blocks to accelerate model construction, enable comprehensive system-level exploration and make system design available for a diverse application space.

These IP blocks are used in VisualSim Architect to assemble system models. The blocks are hardware (A72, Power8, PCIe, DDR4, Cache,
DMA etc.), software (RTOS, Task/Thread), resource (time-based, scheduler-based, quantity-based, queue), traffic (distribution, file input, custom sequence), and supporting components. These blocks have functionality, timing and power information defined.

Key Features

  • Technology IP are built according to the specification from the standard bodies or vendor datasheet
  • Technology IP are accurately modeled for functionality, internal logical flow, buffers, timing, cycle-accuracy and power attributes.
  • IP blocks are validated against timing diagrams and throughput measurements.
  • A significant number of the technology IP blocks are provided with source code. Users can view the internals and modify features including the arbitration schemes, port behavior, error generation and recovery.
  • Each IP contains a unique set of parameters that ensure the user can create all possible variations of the block. For basic blocks, these can be buffer size, scheduler and priority fields. For more complex blocks, they can be Request Threshold, Arbitration, Signal Timing and Clock Speed.
  • All IP blocks are polymorphic and have a standard connectivity mechanism to Masters, Slaves, bridges and other interfaces. There is no need for custom protocol converters between interfaces and devices.
  • The IP blocks are always maintained to the latest version of the standards and provide support for previous versions.
  • There are a number of reports available for each Technology IP block. The standard items include buffer usage, utilization, delays and number dropped. Specialty reports can include the hit-ratio for a cache, processor pipeline stall, the number of IO for a Root Complex and number preempted.

Here is the listing of the Technology IP topics. Click to view detailed information on each of the Technology IP