Solutions for Industry Leaders
VisualSim supports system-level exploration across hardware, software, and physical domains, enabling early bottleneck detection, power and performance analysis, and validation of system behavior under real workloads.
Built-in automation, signal-level visibility, and analytics help teams optimize architectures and reduce pre-development risk.
The Arteris NoC (Network-on-Chip) library package in VisualSim models a scalable and performance-optimized interconnect for SoCs.
The GPU library in VisualSim Architect enables system-level modeling and exploration of modern graphics and compute accelerators, ranging from edge-class GPUs to large-scale data center and AI GPUs.
The ARM architecture model in VisualSim Architect enables cycle-accurate simulation and performance analysis of a wide range of ARM-based processors.
The Task Graph model in VisualSim is the foundation of workload and data movement simulation. It defines how software execution, signal processing, data transfers, and inter-process communications are structured and executed.
Modeling multiple requester with addresses to DDR and LPDDR
Credit-based arbitration for data movement from Ingress to Egress
Model software processes as control and data-flow and map
to hardware topology to study power and timing deadlines
Exploring the implementation of a real-time video
processing on a ARM SoC with hardware accelerators
and power management
Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
Hardware-software mapping of a Radar system for a aircraft.
Designing the Routers and phones to meet quality and performance metrics
Implemented an avionics software on the Quadcore A53 on the Xilinx Ultrascale
