Blogs

AI-Assisted VisualSim Architecture Exploration for Semiconductors and Systems

July 12, 2026

Mirabilis Design introduces the next evolution of VisualSim Architect 2630: an AI-assisted digital engineering environment for semiconductor, SoC, chiplet, data center, and cyber-physical system design. VisualSim helps engineering teams move faster from concept to verified architecture. A modern AI SoC, chiplet platform, avionics system, communication system, automotive controller, or data center accelerator is not a […]

DAC 2026: Architecture Exploration for Semiconductors and Mission-Scale Electronics

July 12, 2026

Visit Mirabilis Design at Booth 761 Semiconductor design is no longer only about building a faster chip. Today’s products must deliver performance, power efficiency, thermal control, software readiness, workload scalability, and system-level reliability before hardware is available. At DAC 2026, Mirabilis Design will demonstrate how VisualSim Architect enables semiconductor and system teams to model, simulate, […]

Why UALink Configuration Needs Real Workload Simulation for LLM Data Centers

June 8, 2026

UALink configuration for AI data centers cannot be selected from bandwidth numbers alone. For LLM workloads, teams must understand how data moves across CPUs, GPUs, XPUs, memory, and interconnects. This article explains how VisualSim Architect uses GPT-style task graphs and digital twin simulation to evaluate latency, power, energy, congestion, and workload performance before hardware is finalized.

Why LLM Workloads Need Smarter AI SoC Design

May 29, 2026

AI workloads are no longer simple compute tasks running on a single processor. Large Language Models move massive amounts of data across GPUs, CPUs, memory, storage, and high-speed interconnects. Every decision— from how workloads are split to which interconnect is used— can affect performance, power, heat, and cost. This is why architecture planning has become […]

Webinar: Optimizing LLM Workload Performance through Selection, Sizing, and Partitioning across AI SoC Interconnects

May 28, 2026

VisualSim Electronics Hackathon 2026 | Semiconductor System Modeling Competition

March 10, 2026

Design and optimize next-generation electronic systems using system-level modeling techniques used by engineers worldwide. Learn. Compete. Build the future of electronics architecture. Registration is now Closed. Thank you for registering. Please wait for more information. Prize Pool Hackathon Date Training Included Career Opportunity $1,000 / ₹90,000 April 12, 2026 (24 hours) March 26 – April […]

Visit Mirabilis Design at Chiplet Summit 2026 — Booth 314

January 25, 2026

The global semiconductor industry is rapidly embracing chiplet-based architectures, heterogeneous integration, high-bandwidth die-to-die fabrics, and system-level co-design. As design complexity increases, engineering teams across compute, networking, AI accelerators, RF, memory, and advanced packaging are demanding faster ways to explore architectures, evaluate trade-offs, and validate system performance before any RTL or silicon investment. At this year’s […]

Mirabilis Design – 2025 Annual Newsletter

January 18, 2026

“What a Year. And Yes… We’re Just Getting Started.” Hello everyone, If 2023 and 2024 were warm-ups, then 2025 was the year Mirabilis Design threw the proverbial kitchen sink at innovation—and somehow managed to launch everything without burning the place down. So grab a coffee (or something stronger). Here’s a fast, fun dive into what […]

VisualSim 2610 System-Level Modeling: New Python, RF, Power, and Multi-Domain Simulation Capabilities

January 18, 2026

Library Features

Build System Models in Days, Not Months

January 15, 2026

Flexible system-level modeling in VisualSim using Python and multiple design methodologies Register Now: January 29 | Two Live Sessions Asia Session🕚 11:30 AM IST | 🕑 2:00 PM CST | 🕒 3:00 PM JST/KST👉 Register:Webinar: 🚀 Start Modeling with Python.Asia US / EMEA Session🕙 10:00 AM PST | 🕐 1:00 PM EST👉 Register:Webinar: 🚀 Start […]

Architecting for Efficiency: Measuring and Managing Power from Chiplet to System

October 21, 2025

Power defines performance. Join Mirabilis Design on November 6 2025 in a Webinar to see how VisualSim Architect lets system architects explore, measure, and optimize power at every stage of design. Direct link to the Webinar: https://youtube.com/shorts/hBaq7_uD4dg Speakers: Deepak Shankar, Founder & Chief Technologist, Mirabilis Design Inc. LinkedIn Profile Overview Across the globe, data centers and high-performance […]

Webinar: Master SoC Architecture Trade-Offs

August 22, 2025

Avoid Million-Dollar Design Mistakes with Early Exploration Date: September 4 2025 Register for Session 1 (APAC): 11:30 AM IST | 2:00 PM CST | 3:00 PM JST/KST: Session1 Register for Session 2 (US): 10:00 AM PST | 1:00 PM EST: Session 2 Speakers Deepak Shankar, Founder, Mirabilis Design Inc. LinkedIn Prakash Sahay, Solutions Group Director, […]

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