Blogs

Webinar: Optimizing LLM Workload Performance through Selection, Sizing, and Partitioning across AI SoC Interconnects

May 28, 2026

VisualSim Electronics Hackathon 2026 | Semiconductor System Modeling Competition

March 10, 2026

Design and optimize next-generation electronic systems using system-level modeling techniques used by engineers worldwide. Learn. Compete. Build the future of electronics architecture. Registration is now Closed. Thank you for registering. Please wait for more information. Prize Pool Hackathon Date Training Included Career Opportunity $1,000 / ₹90,000 April 12, 2026 (24 hours) March 26 – April […]

Visit Mirabilis Design at Chiplet Summit 2026 — Booth 314

January 25, 2026

The global semiconductor industry is rapidly embracing chiplet-based architectures, heterogeneous integration, high-bandwidth die-to-die fabrics, and system-level co-design. As design complexity increases, engineering teams across compute, networking, AI accelerators, RF, memory, and advanced packaging are demanding faster ways to explore architectures, evaluate trade-offs, and validate system performance before any RTL or silicon investment. At this year’s […]

Mirabilis Design – 2025 Annual Newsletter

January 18, 2026

“What a Year. And Yes… We’re Just Getting Started.” Hello everyone, If 2023 and 2024 were warm-ups, then 2025 was the year Mirabilis Design threw the proverbial kitchen sink at innovation—and somehow managed to launch everything without burning the place down. So grab a coffee (or something stronger). Here’s a fast, fun dive into what […]

VisualSim 2610 System-Level Modeling: New Python, RF, Power, and Multi-Domain Simulation Capabilities

January 18, 2026

Library Features

Build System Models in Days, Not Months

January 15, 2026

Flexible system-level modeling in VisualSim using Python and multiple design methodologies Register Now: January 29 | Two Live Sessions Asia Session🕚 11:30 AM IST | 🕑 2:00 PM CST | 🕒 3:00 PM JST/KST👉 Register:Webinar: 🚀 Start Modeling with Python.Asia US / EMEA Session🕙 10:00 AM PST | 🕐 1:00 PM EST👉 Register:Webinar: 🚀 Start […]

Architecting for Efficiency: Measuring and Managing Power from Chiplet to System

October 21, 2025

Power defines performance. Join Mirabilis Design on November 6 2025 in a Webinar to see how VisualSim Architect lets system architects explore, measure, and optimize power at every stage of design. Direct link to the Webinar: https://youtube.com/shorts/hBaq7_uD4dg Speakers: Deepak Shankar, Founder & Chief Technologist, Mirabilis Design Inc. LinkedIn Profile Overview Across the globe, data centers and high-performance […]

Webinar: Master SoC Architecture Trade-Offs

August 22, 2025

Avoid Million-Dollar Design Mistakes with Early Exploration Date: September 4 2025 Register for Session 1 (APAC): 11:30 AM IST | 2:00 PM CST | 3:00 PM JST/KST: Session1 Register for Session 2 (US): 10:00 AM PST | 1:00 PM EST: Session 2 Speakers Deepak Shankar, Founder, Mirabilis Design Inc. LinkedIn Prakash Sahay, Solutions Group Director, […]

July 2025: Driving Innovation: VisualSim Hits the Road, the Classroom, and Industry

August 1, 2025

Mirabilis Design Newsletter 2025 Founder’s Note I hope you’re enjoying a wonderful summer! At Mirabilis Design, AI is taking center stage — helping us track dynamic behavior during simulation and detecting performance bottlenecks, thus maximizing the role of system modeling. By integrating VisualSim into the broader EDA workflow through co-simulations and more parameters for system components, we’re […]

Optimizing Automotive Electronics Architecture for Autonomous and Electric Vehicles Using System-Level Modeling

June 16, 2025

Author: Deepak Shankar, Vice President Technology, Mirabilis Design Inc. Introduction The rapid adoption of autonomous driving technologies and electric vehicles (EVs) has fundamentally shifted automotive electronics design. As AI-based functionalities proliferate across vehicle subsystems, system architects face increasing complexity in balancing performance, power efficiency, and hardware costs. Traditional design approaches relying on spreadsheets and analytical […]

RISC-V architecture exploration using VisualSim Architect.

June 6, 2025

Abstract The RISC-V architecture offers unparalleled flexibility in processor design, allowing custom instruction sets, memory hierarchies, and peripheral configurations. This study presents a model-driven approach using VisualSim Architect to explore the performance, power, and functional trade-offs of RISC-V cores in complex system-on-chip (SoC) environments. We simulate multiple RISC-V microarchitectures with configurable pipeline stages, cache hierarchies, […]

Architecture Exploration of ARM-based SoC and Chiplets

March 15, 2025

Unlocking Optimal Power and Performance: A Deep Dive into ARM SoC Modeling Webinar link: https://youtu.be/RBw5ifzuIHA In the competitive world of semiconductor design, balancing power consumption with high performance is a constant challenge. With VisualSim Architect, engineers can simulate intricate ARM-based SoCs with unparalleled accuracy, paving the way for innovative, power-efficient solutions. The Future of SoC […]

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