Date and Time
Mirabilis Design will host a live webinar on June 16 with two sessions to support global attendees.
Asia Session
June 16 | 1:00 PM IST | 4:30 PM JST/KST | 2:30 PM China | 9:30 AM CEST
Register here: Link
US / EMEA Session
June 16 | 10:00 AM PST | 1:00 PM EST | 5:00 PM BST
Register here: Link
What Is This Webinar About?
Large Language Model workloads are changing how AI systems are designed. These workloads move large amounts of data across compute, memory, accelerators, and high-speed interconnects. As a result, performance is no longer based only on the speed of one processor or accelerator. It depends on how well the entire system works together.
Architecture teams now need to answer important questions much earlier in the design cycle. Which interconnect should be used? How much memory is required? Where should workloads be partitioned? How do teams reduce latency without increasing power and heat? How can hardware be sized correctly without overbuilding the system?
This webinar will show how VisualSim Architect helps answer these questions using early digital twin modeling. By creating a system-level model before hardware is finalized, teams can evaluate LLM workload behavior across CXL memory, NVLink, PCIe, and UALink. This makes it possible to compare design options, find bottlenecks, and make better architecture decisions earlier.
The session will also show how VisualSim supports the selection, sizing, and partitioning of workloads across AI SoC interconnects. Instead of waiting for late-stage implementation results, teams can explore the impact of each design choice on performance, power, heat, and utilization during the architecture phase.
Speaker
Kesudh Giri
AI R&D Engineer
Mirabilis Design Inc.
Kesudh Giri is an AI R&D Engineer at Mirabilis Design, designing IP libraries for semiconductor companies to make architectural decisions for AI SoCs and high-performance compute platforms. His work focuses on modeling interconnects, memory, and compute fabrics to evaluate performance, power, and scalability trade-offs early in the design cycle.
Who Should Attend?
This webinar is designed for teams working on next-generation AI systems, semiconductor platforms, and high-performance computing architectures.
It is especially useful for:
System architects
– AI SoC design teams
– Performance engineering teams
– Semiconductor engineering teams
– Data center architecture teams
– Accelerator and memory system teams
– Hardware/software partitioning teams
– Teams evaluating CXL, NVLink, PCIe, or UALink-based designs
If your team is working on AI infrastructure, LLM acceleration, workload partitioning, or interconnect trade-offs, this session will provide a practical view of how early simulation can improve design confidence.
Advantages of Attending
The main advantage of this webinar is learning how to move important architecture decisions earlier in the design process.
With VisualSim Architect, teams can create a digital twin of the system and test different design choices before committing to hardware. This helps reduce guesswork and provides measurable results for performance, latency, power, heat, and resource utilization.
Attendees will see how VisualSim can help teams:
- Compare AI SoC interconnect options
- Evaluate CXL memory, NVLink, PCIe, and UALink trade-offs
- Improve workload partitioning across compute and memory resources
- Identify bottlenecks before hardware is finalized
- Reduce over-provisioning and unnecessary cost
- Analyze power and thermal impact early
- Improve overall system utilization
- Support better performance-per-watt decisions
This approach helps teams make architecture decisions with more confidence and reduces the risk of discovering major issues too late in the design cycle.
What Will You Learn?
In this webinar, attendees will learn how VisualSim Architect can be used to model LLM workloads and evaluate how those workloads behave across AI SoC interconnects.
The session will explain how digital twin modeling can be used to test different system configurations, study workload movement, compare interconnect choices, and understand the relationship between performance, power, and heat.
You will learn how to:
- Model LLM workload behavior at the system level
- Evaluate workload selection, sizing, and partitioning
- Compare CXL memory, NVLink, PCIe, and UALink trade-offs
- Analyze performance bottlenecks across compute and memory fabrics
- Study the impact of interconnect decisions on latency and utilization
- Understand how power and heat change as workloads scale
- Use early simulation results to guide architecture decisions
The goal is to give attendees a clear, practical understanding of how VisualSim helps teams design better AI SoC and high-performance compute platforms before implementation begins.
Register Here
Join Mirabilis Design on June 16 to learn how VisualSim Architect can help optimize LLM workload performance through early digital twin modeling.
Asia Session
1:00 PM IST | 4:30 PM JST/KST | 2:30 PM China | 9:30 AM CEST
Register here: Link
US / EMEA Session
10:00 AM PST | 1:00 PM EST | 6:00 PM BST
Register here: Link
