Digital Signal Processor

Model of a TI C64x DSP

Integrated_DSP_ARM_Platform_wout_DMA

Browsable image of the model.

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<h2>MPMC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Sim_Time</td><td>1.0 /*Sim_Time*/</td><td>1.0</td></tr><tr><td>MPMC_Speed_Mhz</td><td>400.0</td><td>400.0</td></tr><tr><td>MPMC_Pipeline_Slots</td><td>4 /*  Max 8 */</td><td>4</td></tr><tr><td>MPMC_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>MPMC_Plotting_Destination</td><td>&quot;MyPlot&quot; /* &quot;none&quot; turns off */</td><td>&quot;MyPlot&quot;</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Xilinx_FPGA-&gt;MPMC_Mem_Ctrl</td><td>Hardware_Modeling-&gt;Xilinx_FPGA-&gt;MPMC_Mem_Ctrl</td></tr></table> <h2>Architecture_Setup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nC64\t\tSDRAM_2\t\t  SDRAM_2\tbus_out     ;\\nSDRAM_2\t   \tC64\t\t  C64\t    \toutput\t    ;\\nEthernet_DMA    IO_3              IO_3          output      ;\\nPCI_DMA         IO_4              IO_4          output      ;\\nARM7_1          C64               Port_13       instr_out   ;\\nPort_13\t\tC64\t\t  Port_14\tPort_13\t    ;\\nPort_14\t\tC64\t\t  Port_14\tPort_14\t    ;\\nC64             ARM7_1            Port_14       instr_out   ;\\nPort_14\t\tARM7_1\t\t  Port_13\tPort_14\t    ;\\nPort_13\t\tARM7_1\t\t  Port_13\tPort_13     ;</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nC64\t\tSDRAM_2\t\t  SDRAM_2\tbus_out     ;\\nSDRAM_2\t   \tC64\t\t  C64\t    \toutput\t    ;\\nEthernet_DMA    IO_3              IO_3          output      ;\\nPCI_DMA         IO_4              IO_4          output      ;\\nARM7_1          C64               Port_13       instr_out   ;\\nPort_13\t\tC64\t\t  Port_14\tPort_13\t    ;\\nPort_14\t\tC64\t\t  Port_14\tPort_14\t    ;\\nC64             ARM7_1            Port_14       instr_out   ;\\nPort_14\t\tARM7_1\t\t  Port_13\tPort_14\t    ;\\nPort_13\t\tARM7_1\t\t  Port_13\tPort_13     ;</td></tr><tr><td>Number_of_Samples</td><td>10</td><td>10</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;ARM7_1_PROC_Utilization_Pct_Mean, ARM7_2_PROC_Utilization_Pct_Mean,C64_PROC_Utilization_Pct_Mean,AHB_1_Utilization_Pct_Mean,AHB_2_Utilization_Pct_Mean&quot;</td><td>&quot;ARM7_1_PROC_Utilization_Pct_Mean, ARM7_2_PROC_Utilization_Pct_Mean,C64_PROC_Utilization_Pct_Mean,AHB_1_Utilization_Pct_Mean,AHB_2_Utilization_Pct_Mean&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>SDRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Memory_Name</td><td>SDRAM_Name</td><td>&quot;SDRAM_2&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>MPMC_Speed_Mhz</td><td>400.0</td></tr><tr><td>Memory_Size_MBytes</td><td>SDRAM_MBytes</td><td>1000.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 2.0, Prefetch 3.0, Write 2.0, ReadWrite 4.0, Erase 5.0&quot;</td><td>&quot;Read 2.0, Prefetch 3.0, Write 2.0, ReadWrite 4.0, Erase 5.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>SDRAM_FIFO_Buffers</td><td>64</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384000</td><td>16384000</td></tr><tr><td>Refresh_Cycles</td><td>16</td><td>16</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR2</td><td>DDR2</td></tr></table> <h2>Local_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Arch_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>33.0</td><td>33.0</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.0E-3</td></tr></table> <h2>Task_Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Database2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase_2&quot;</td><td>&quot;DMADatabase_2&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMyTask2         ADD\t        0\tSDRAM_1\t        8 \t        1               0\t        0\t        Read\t        8 \t0\t        PCI_DMA          \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMyTask2         ADD\t        0\tSDRAM_1\t        8 \t        1               0\t        0\t        Read\t        8 \t0\t        PCI_DMA          \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase_1&quot;</td><td>&quot;DMADatabase_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source  Burst_Word_Size\tA_Task_Address  A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMyTask\t        ADD\t        0\tSDRAM_1\t       8\t        1               0\t        0\t        Read\t        8\t0\t        Ethernet_DMA     \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source  Burst_Word_Size\tA_Task_Address  A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMyTask\t        ADD\t        0\tSDRAM_1\t       8\t        1               0\t        0\t        Read\t        8\t0\t        Ethernet_DMA     \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>State_Plot</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Proc_Name</td><td>&quot;C64&quot;</td><td>&quot;C64&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_4&quot;</td><td>&quot;Bus_4&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_4&quot;</td><td>&quot;Cache_4&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM_2&quot;</td><td>&quot;SDRAM_2&quot;</td></tr></table> <h2>Instr_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;C64_Instr&quot;</td><td>&quot;C64_Instr&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n   Mnew Ra  Rb  Rc  Rd   Re ;   /* Label */\\n   DSP  LUnit MUnit SUnit DUnit         ;\\n   LUnit  INT_1 INT_2         \t\t;\\n   MUnit  INT_3 INT_4               \t;\\n   SUnit  INT_5 INT_6                \t;\\n   DUnit  INT_7 INT_8\t\t\t;\\n\\nbegin INT_7                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV   1 ;\\nOR   1 ;\\nSTB  1 ;\\nLDB   5 ;\\nSUB  1 ;\\nXOR  1 ;\\nZERO 1 ;\\nend   INT_7                 ;\\n\\nbegin INT_8                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV   1 ;\\nOR   1 ;\\nSTB  1 ;\\nLDB   5 ;\\nSUB  1 ;\\nXOR  1 ;\\nZERO 1 ;\\nend   INT_8                 ;\\n\\nbegin INT_3                 ;   /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL  2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD  4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend   INT_3                 ;\\n\\nbegin INT_4                 ;   /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL  2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD  4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend   INT_4                 ;\\n\\nbegin INT_5                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B  5 ;\\nDMV  1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL  1 ;\\nMV  1 ;\\nSHR  1 ; \\nNEG 1 ;\\nOR  1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4  1 ;\\nXOR 1 ;\\nZERO  1 ;\\nend   INT_5                  ;\\n\\nbegin INT_6                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B  5 ;\\nDMV  1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL  1 ;\\nMV  1 ;\\nSHR  1 ; \\nNEG 1 ;\\nOR  1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4  1 ;\\nXOR 1 ;\\nZERO  1 ;\\nend   INT_6                  ;\\n\\nbegin INT_1                  ;   /* Group */\\nADD 1 ;\\nABS 1  ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV  1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT  1 ; \\nOR  1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO  1 ;\\nLMBD  1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend   INT_1                  ;\\n\\nbegin INT_2                  ;   /* Group */\\nADD 1 ;\\nABS 1  ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV  1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT  1 ; \\nOR  1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO  1 ;\\nLMBD  1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend   INT_2                  ;</td><td>/* Instruction Set or File Path. */\\n   Mnew Ra  Rb  Rc  Rd   Re ;   /* Label */\\n   DSP  LUnit MUnit SUnit DUnit         ;\\n   LUnit  INT_1 INT_2         \t\t;\\n   MUnit  INT_3 INT_4               \t;\\n   SUnit  INT_5 INT_6                \t;\\n   DUnit  INT_7 INT_8\t\t\t;\\n\\nbegin INT_7                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV   1 ;\\nOR   1 ;\\nSTB  1 ;\\nLDB   5 ;\\nSUB  1 ;\\nXOR  1 ;\\nZERO 1 ;\\nend   INT_7                 ;\\n\\nbegin INT_8                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV   1 ;\\nOR   1 ;\\nSTB  1 ;\\nLDB   5 ;\\nSUB  1 ;\\nXOR  1 ;\\nZERO 1 ;\\nend   INT_8                 ;\\n\\nbegin INT_3                 ;   /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL  2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD  4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend   INT_3                 ;\\n\\nbegin INT_4                 ;   /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL  2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD  4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend   INT_4                 ;\\n\\nbegin INT_5                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B  5 ;\\nDMV  1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL  1 ;\\nMV  1 ;\\nSHR  1 ; \\nNEG 1 ;\\nOR  1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4  1 ;\\nXOR 1 ;\\nZERO  1 ;\\nend   INT_5                  ;\\n\\nbegin INT_6                 ;   /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B  5 ;\\nDMV  1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL  1 ;\\nMV  1 ;\\nSHR  1 ; \\nNEG 1 ;\\nOR  1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4  1 ;\\nXOR 1 ;\\nZERO  1 ;\\nend   INT_6                  ;\\n\\nbegin INT_1                  ;   /* Group */\\nADD 1 ;\\nABS 1  ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV  1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT  1 ; \\nOR  1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO  1 ;\\nLMBD  1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend   INT_1                  ;\\n\\nbegin INT_2                  ;   /* Group */\\nADD 1 ;\\nABS 1  ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV  1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT  1 ; \\nOR  1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO  1 ;\\nLMBD  1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend   INT_2                  ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name2&quot;</td><td>&quot;Record_Set_Name2&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>TI-C64</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DSP_Speed</td><td>400.0</td><td>400.0</td></tr><tr><td>Mem_Name</td><td>SDRAM_Name</td><td>&quot;SDRAM_2&quot;</td></tr><tr><td>Arch_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>DSP_Name</td><td>&quot;C64&quot;</td><td>&quot;C64&quot;</td></tr></table> <h2>Scheduler</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Arch_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr></table> <h2>State_Plot_Block2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Proc_Name</td><td>&quot;ARM7_2&quot;</td><td>&quot;ARM7_2&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_2&quot;</td><td>&quot;Bus_2&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_L2&quot;</td><td>&quot;Cache_L2&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr></table> <h2>State_Plot_Block</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Proc_Name</td><td>&quot;ARM7_1&quot;</td><td>&quot;ARM7_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_L2&quot;</td><td>&quot;Cache_L2&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr></table> <h2>Dual_ARM_7</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Processor_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>66.0</td></tr><tr><td>Cache_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>66.0</td></tr><tr><td>Cache_Size_KB</td><td>32</td><td>32</td></tr><tr><td>I_Cache_KB</td><td>&quot;16&quot;</td><td>&quot;16&quot;</td></tr><tr><td>D_Cache_KB</td><td>&quot;8&quot;</td><td>&quot;8&quot;</td></tr><tr><td>RAM_Speed_Mhz</td><td>Processor_Speed_Mhz / 2.0</td><td>33.0</td></tr><tr><td>Bus_Speed_Mhz</td><td>33.0</td><td>33.0</td></tr><tr><td>RAM_Size_MB</td><td>8</td><td>8</td></tr><tr><td>RAM_Access_Time</td><td>&quot;Read 8.0,Prefetch 8.0,Refresh 8.0,Write 7.5&quot;</td><td>&quot;Read 8.0,Prefetch 8.0,Refresh 8.0,Write 7.5&quot;</td></tr><tr><td>Arch_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.0E-3</td></tr></table> <h2>Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM7_INSTR&quot;</td><td>&quot;ARM7_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM7 TDMI pdf. */\\n\\n   Mnew Arg1  Arg2  Arg3     ; /* Label               */\\n   ARM7 INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n\\n   ART_ADD 1  4              ; /* group ARITHMETIC */\\n   last_round_add 1 4        ;\\n   ART_ADC 1  4              ;\\n   ART_SUB 1  4              ;\\n   ART_SBC 1  4              ;\\n   ART_RSB 1  4              ;\\n   ART_RSC 1  4              ;\\n   ART_MUL 2  3              ;\\n   ART_MLA 2  3              ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   eor     1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   ldr     1 5               ; /* group LOAD */\\n   lsr     1 5               ;\\n   ldr_rcon  4               ;\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n   #MOVE_OP 1\t\t     ;  /*Instruction to send request to DSP */\\n\\nend   INT_1                  ;\\n</td><td>/* Instruction Set : Reference ARM7 TDMI pdf. */\\n\\n   Mnew Arg1  Arg2  Arg3     ; /* Label               */\\n   ARM7 INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n\\n   ART_ADD 1  4              ; /* group ARITHMETIC */\\n   last_round_add 1 4        ;\\n   ART_ADC 1  4              ;\\n   ART_SUB 1  4              ;\\n   ART_SBC 1  4              ;\\n   ART_RSB 1  4              ;\\n   ART_RSC 1  4              ;\\n   ART_MUL 2  3              ;\\n   ART_MLA 2  3              ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   eor     1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   ldr     1 5               ; /* group LOAD */\\n   lsr     1 5               ;\\n   ldr_rcon  4               ;\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n   #MOVE_OP 1\t\t     ;  /*Instruction to send request to DSP */\\n\\nend   INT_1                  ;\\n</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set&quot;</td><td>&quot;Record_Set&quot;</td></tr></table> <h2>Display_Text</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Title</td><td>&quot;Statistics Summary&quot;</td><td>&quot;Statistics Summary&quot;</td></tr><tr><td>Lines_Buffered</td><td>5</td><td>5</td></tr><tr><td>Rows_Displayed</td><td>15</td><td>15</td></tr><tr><td>Columns_Displayed</td><td>75</td><td>75</td></tr><tr><td>Font_Type</td><td>Lucida Console</td><td>Lucida Console</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Utilization</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>ARM_1mean,ARM_2mean,C64_mean,AHB1,AHB2</td><td>ARM_1mean,ARM_2mean,C64_mean,AHB1,AHB2</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table>

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