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RISC-V SIMD

RISC_V model execution the NP Benchmark tasks

RISCV_InOrder

Below is a browsable image of the model.

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    Windows– Compatibility:Windows 10 or higher (*)
    macOS – Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux – Compatibility:Ubuntu 18.04 LTS or higher (*)
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<h2>RISC-V ISA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;RISCV_ISA&quot;</td><td>&quot;RISCV_ISA&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\nMnew Ra Rb Rc Rd Re Rf\t\t\t; /* Label */\\nRISCV INT_1 INT_2 INT_3 INT_4 INT_5 FP_1\t;\\n\\n/*\\nINT_1 - Arithmetic I\\nINT_2 - Arithmetic II\\nINT_3 - Load/Store\\nINT_4 - Branching\\nINT_5 - Logic, Shift, Move\\nFP_1 - Floating Point\\n*/\\n\\nbegin INT_1\t\t;\\n\tADD 1\t\t; \\n\tADDI 1\t\t; /*Add Immediate*/\t\\n\tSUB 1\t\t;\\nend INT_1\t\t;\t\t\\n\\nbegin INT_2\t\t;\\n\tMUL 2\t\t;\\n\tMULH 2\t\t;\\n\tMULHU 2\t\t;\\n\tMULHSU 2\t;\\n\tDIV 2 33\t;\\n\tDIVU 2 33\t; /*Divide Unsigned*/\t\\n\tREM 2 33\t;\\n\tREMU 2 33\t; /*Remainder Unsigned*/\t\\nend INT_2\t\t;\\n\\nbegin INT_3\t\t;\\n\tLW 2\t\t; /*Load Word*/\\n\tLH 3\t\t; /*Load HalfWord*/\\n\tSW 2\t\t; /*Store Word*/\\n\tSH 3\t\t; /*Store HalfWord*/\\n\t#LW_DMA 2\t;\t\\n\t#SW_DMA 2\t;\\nend INT_3\t\t;\\n\\nbegin INT_4\t\t;\\n\tBEQ 3\t\t; /*Branch = */\\n\tBNE 3\t\t; /*Branch != */\\n\tBLT 3\t\t; /*Branch &lt; */\\n\tBGE 3\t\t; /*Branch &gt;= */\\n\tJMP 3\t\t; /*Jump*/\\n\t*JMP 3\t\t; /*Mispredict*/\\nend INT_4\t\t;\\n\\nbegin INT_5\t\t;\\n\tOR 2\t\t; \\n\tORI 2\t\t; /*OR Immediate*/\\n\tAND 2\t\t; \\n\tANDI 2\t\t; /*AND Immediate*/\\n\tXOR 2\t\t; \t\\n\tXORI 2\t\t; /*XOR Immediate*/\\n\tSLL 1\t\t; /*Logical Left Shift*/\\n\tSLLI 1\t\t; /*Logical Left Shift Immediate*/\\n\tSRL 1\t\t; /*Logical Right Shift*/\\n\tSRLI 1\t\t; /*Logical Right Shift Immediate*/\\n\tSRA 1\t\t; /*Arithmetic Right Shift*/\\n\tMOV 1\t\t;\\nend INT_5\t\t;\\n\\nbegin FP_1\t\t;\\n\tFL 2\t\t; /*FP Load*/\\n\tFS 2\t\t; /*FP Store*/\\n\tFADD 3\t\t; /*FP Add*/\\n\tFSUB 3\t\t; /*FP Sub*/\\n\tFMUL 3\t\t; /*FP Mult*/\\n\tFDIV 3 17\t\t; /*FP Div*/\\n\tFCVT 5\t\t; /*Convert from Int*/\\n\tFCVT_W 5\t; /*Convert to Int*/\\nend FP_1\t\t;</td><td>/* Instruction Set or File Path. */\\nMnew Ra Rb Rc Rd Re Rf\t\t\t; /* Label */\\nRISCV INT_1 INT_2 INT_3 INT_4 INT_5 FP_1\t;\\n\\n/*\\nINT_1 - Arithmetic I\\nINT_2 - Arithmetic II\\nINT_3 - Load/Store\\nINT_4 - Branching\\nINT_5 - Logic, Shift, Move\\nFP_1 - Floating Point\\n*/\\n\\nbegin INT_1\t\t;\\n\tADD 1\t\t; \\n\tADDI 1\t\t; /*Add Immediate*/\t\\n\tSUB 1\t\t;\\nend INT_1\t\t;\t\t\\n\\nbegin INT_2\t\t;\\n\tMUL 2\t\t;\\n\tMULH 2\t\t;\\n\tMULHU 2\t\t;\\n\tMULHSU 2\t;\\n\tDIV 2 33\t;\\n\tDIVU 2 33\t; /*Divide Unsigned*/\t\\n\tREM 2 33\t;\\n\tREMU 2 33\t; /*Remainder Unsigned*/\t\\nend INT_2\t\t;\\n\\nbegin INT_3\t\t;\\n\tLW 2\t\t; /*Load Word*/\\n\tLH 3\t\t; /*Load HalfWord*/\\n\tSW 2\t\t; /*Store Word*/\\n\tSH 3\t\t; /*Store HalfWord*/\\n\t#LW_DMA 2\t;\t\\n\t#SW_DMA 2\t;\\nend INT_3\t\t;\\n\\nbegin INT_4\t\t;\\n\tBEQ 3\t\t; /*Branch = */\\n\tBNE 3\t\t; /*Branch != */\\n\tBLT 3\t\t; /*Branch &lt; */\\n\tBGE 3\t\t; /*Branch &gt;= */\\n\tJMP 3\t\t; /*Jump*/\\n\t*JMP 3\t\t; /*Mispredict*/\\nend INT_4\t\t;\\n\\nbegin INT_5\t\t;\\n\tOR 2\t\t; \\n\tORI 2\t\t; /*OR Immediate*/\\n\tAND 2\t\t; \\n\tANDI 2\t\t; /*AND Immediate*/\\n\tXOR 2\t\t; \t\\n\tXORI 2\t\t; /*XOR Immediate*/\\n\tSLL 1\t\t; /*Logical Left Shift*/\\n\tSLLI 1\t\t; /*Logical Left Shift Immediate*/\\n\tSRL 1\t\t; /*Logical Right Shift*/\\n\tSRLI 1\t\t; /*Logical Right Shift Immediate*/\\n\tSRA 1\t\t; /*Arithmetic Right Shift*/\\n\tMOV 1\t\t;\\nend INT_5\t\t;\\n\\nbegin FP_1\t\t;\\n\tFL 2\t\t; /*FP Load*/\\n\tFS 2\t\t; /*FP Store*/\\n\tFADD 3\t\t; /*FP Add*/\\n\tFSUB 3\t\t; /*FP Sub*/\\n\tFMUL 3\t\t; /*FP Mult*/\\n\tFDIV 3 17\t\t; /*FP Div*/\\n\tFCVT 5\t\t; /*Convert from Int*/\\n\tFCVT_W 5\t; /*Convert to Int*/\\nend FP_1\t\t;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr></table> <h2>Power Inst</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>RISCV_InOrder_Power.plt</td><td>&quot;RISCV_InOrder_Power.plt&quot;</td></tr><tr><td>viewPlot</td><td>false</td><td>false</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Plots</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>L2 Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;L2&quot;</td><td>&quot;L2&quot;</td></tr><tr><td>Miss_Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Cache_Speed_Mhz</td><td>ClockRate</td><td>500.0</td></tr><tr><td>Cache_Size_KBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Words_per_Cache_Line</td><td>8</td><td>8</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Cache_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td></tr><tr><td>Cache_Hit_Expression</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Task Generator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>VariableList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template \\nName Type Value */\\nT1 Global 0.0\\nCPI\t Global\t 0.0\\n</td><td>/* Memory Initialize Template \\nName Type Value */\\nT1 Global 0.0\\nCPI\t Global\t 0.0\\n</td></tr></table> <h2>RISC-V Core</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;RISC_V_InOrder&quot;</td><td>&quot;RISC_V_InOrder&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: RISCV_ISA\\nNumber_of_Registers: 32\\nProcessor_Speed_Mhz: ClockRate\\nContext_Switch_Cycles: 8\\nInstruction_Queue_Length: 32\\nNumber_of_Pipeline_Stages: 5 \\nNumber_of_INT_Execution_Units: 5 \\nNumber_of_FP_Execution_Units: 1 \\nMemory_Database_Reference: DMADatabase\\nNumber_of_Cache_Execution_Units: 2 \\nI_1: {Cache_Speed_Mhz=ClockRate, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=ClockRate, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: RISCV_ISA\\nNumber_of_Registers: 32\\nProcessor_Speed_Mhz: ClockRate\\nContext_Switch_Cycles: 8\\nInstruction_Queue_Length: 32\\nNumber_of_Pipeline_Stages: 5 \\nNumber_of_INT_Execution_Units: 5 \\nNumber_of_FP_Execution_Units: 1 \\nMemory_Database_Reference: DMADatabase\\nNumber_of_Cache_Execution_Units: 2 \\nI_1: {Cache_Speed_Mhz=ClockRate, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=ClockRate, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\n</td></tr><tr><td>Pipeline_Stages</td><td>/* First row contains Column Names. */\\nStage_Name Execution_Location Action Condition ; \\n1_PREFETCH I_1 instr none ; \\n1_PREFETCH D_1 read none ; \\n2_DECODE I_1 wait none ; \\n3_EXECUTE D_1 wait none ; \\n3_EXECUTE RISCV exec none ; \\n4_MEMACC RISCV wait none ; \\n5_STORE D_1 write none ; \\n</td><td>/* First row contains Column Names. */\\nStage_Name Execution_Location Action Condition ; \\n1_PREFETCH I_1 instr none ; \\n1_PREFETCH D_1 read none ; \\n2_DECODE I_1 wait none ; \\n3_EXECUTE D_1 wait none ; \\n3_EXECUTE RISCV exec none ; \\n4_MEMACC RISCV wait none ; \\n5_STORE D_1 write none ; \\n</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table> <h2>BusInterface3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_Name_5&quot;</td><td>&quot;Port_Name_5&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_Name_6&quot;</td><td>&quot;Port_Name_6&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Power Table</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td></tr><tr><td>Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Manager_Setup</td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n where &quot;Scheduler_&quot; or &quot;STR_&quot; + BlockName; Processor, Bus, DRAM = Architecture_Name + &quot;_&quot; + BlockName \\n--------Device Name------- ---------Power States------ \t-----Operating States------ --toActive-- --Speed-- --Exist-- */\\nArchitecture_Block Standby Active Wait Idle Sleep Existing OffState OnState t_OnOff Mhz Volts ; \\nArchitecture_1_RISC_V_InOrder stdb act wait idle slp\t Standby Standby Active Cycle_t ClockRate 1.0 ; \\n\\n</td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n where &quot;Scheduler_&quot; or &quot;STR_&quot; + BlockName; Processor, Bus, DRAM = Architecture_Name + &quot;_&quot; + BlockName \\n--------Device Name------- ---------Power States------ \t-----Operating States------ --toActive-- --Speed-- --Exist-- */\\nArchitecture_Block Standby Active Wait Idle Sleep Existing OffState OnState t_OnOff Mhz Volts ; \\nArchitecture_1_RISC_V_InOrder stdb act wait idle slp\t Standby Standby Active Cycle_t ClockRate 1.0 ; \\n\\n</td></tr><tr><td>Async_State_Change</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n where State to same State can extend a Power State \\n--------Device Name------- --Start------Expression------Next--- */\\nArchitecture_Block State Time State ; \\nArchitecture_1_RISC_V_InOrder Standby 1.0e-7 \t Sleep ;</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n where State to same State can extend a Power State \\n--------Device Name------- --Start------Expression------Next--- */\\nArchitecture_Block State Time State ; \\nArchitecture_1_RISC_V_InOrder Standby 1.0e-7 \t Sleep ;</td></tr><tr><td>Expression_List</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- --------------Expression------------ */\\nName Value ; \\nCycle_t \t0\t \t; \\nstdb\t\t\t\t0.1*act\t\t\t\t;\\nact\t\t\t\t26.28*Mhz\t\t\t;\\nwait\t\t\t\t0.95*act\t\t\t;\\nidle\t\t\t\t0.25*act\t\t\t;\t\t\\nslp\t\t\t\t0.02*act\t\t\t;\t\t</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- --------------Expression------------ */\\nName Value ; \\nCycle_t \t0\t \t; \\nstdb\t\t\t\t0.1*act\t\t\t\t;\\nact\t\t\t\t26.28*Mhz\t\t\t;\\nwait\t\t\t\t0.95*act\t\t\t;\\nidle\t\t\t\t0.25*act\t\t\t;\t\t\\nslp\t\t\t\t0.02*act\t\t\t;\t\t</td></tr><tr><td>Battery_Units</td><td>Micro_Watts</td><td>Micro_Watts</td></tr><tr><td>State_Plot_Enable</td><td>true</td><td>true</td></tr></table> <h2>Power Avg</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>RISCV_InOrder_Power.plt</td><td>&quot;RISCV_InOrder_Power.plt&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>DMADatabase</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination ;\\nTask_1\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_2\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_3\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_4\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_5\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_6\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_7\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_8\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_9\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_10\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_1\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_2\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_3\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_4\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_5\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_6\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_7\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_8\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_9\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_10\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination ;\\nTask_1\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_2\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_3\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_4\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_5\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_6\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_7\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_8\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_9\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_10\t LW_DMA\t 0\t DRAM\t 32\t 1 Read\t 32\t 0\t DMA ;\\nTask_1\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_2\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_3\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_4\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_5\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_6\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_7\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_8\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_9\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;\\nTask_10\t SW_DMA\t 0\t DRAM\t 32\t 1 Write 32\t 0\t DMA ;</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>Integer</td><td>&quot;Integer&quot;</td></tr><tr><td>Speed_Mhz</td><td>500.0</td><td>&quot;500.0&quot;</td></tr><tr><td>DMA_Channels</td><td>1</td><td>1</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr></table> <h2>BusInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_Name_3&quot;</td><td>&quot;Port_Name_3&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_Name_4&quot;</td><td>&quot;Port_Name_4&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>RAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>ClockRate/2</td><td>250.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 4.0, Prefetch 6.0, Write 5.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 4.0, Prefetch 6.0, Write 5.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>DDR3</td><td>DDR3</td></tr></table> <h2>BusInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_Name_1&quot;</td><td>&quot;Port_Name_1&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_Name_2&quot;</td><td>&quot;Port_Name_2&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>BusArbiter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>_explanation</td><td>HardwareDevices-&gt;BusArbiter</td><td>HardwareDevices-&gt;BusArbiter</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>ClockRate/2</td><td>250.0</td></tr><tr><td>Burst_Size_Bytes</td><td>100</td><td>100</td></tr><tr><td>Round_Robin_Port_Array</td><td>{&quot;Port_1&quot;, &quot;Port_2&quot;}</td><td>{&quot;Port_1&quot;, &quot;Port_2&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Arbiter_Mode</td><td>FCFS</td><td>FCFS</td></tr><tr><td>Split_Retry_Flag</td><td>false</td><td>false</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Source_Node Destination_Node Hop Source_Port ; \\nProcessor_1 Cache_1 Port_1 bus_out2 ;\\nCache_1 Processor_1 Port_2 output ;\\nCache_1 SDRAM_1 Port_2 output ;\\nSDRAM_1 Cache_1 Port_4 output ;\\nSDRAM_1 Processor_1 Port_4 output ;</td><td>Source_Node Destination_Node Hop Source_Port ; \\nProcessor_1 Cache_1 Port_1 bus_out2 ;\\nCache_1 Processor_1 Port_2 output ;\\nCache_1 SDRAM_1 Port_2 output ;\\nSDRAM_1 Cache_1 Port_4 output ;\\nSDRAM_1 Processor_1 Port_4 output ;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */</td><td>/* First row contains Column Names. */</td></tr><tr><td>Number_of_Samples</td><td>8</td><td>8</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;RISC_V_Inorder_PROC_Utilization_Min, RISC_V_Inorder_PROC_Utilization_Mean, RISC_V_Inorder_PROC_Utilization_Max&quot;</td><td>&quot;RISC_V_Inorder_PROC_Utilization_Min, RISC_V_Inorder_PROC_Utilization_Mean, RISC_V_Inorder_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table>

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