The global semiconductor industry is rapidly embracing chiplet-based architectures, heterogeneous integration, high-bandwidth die-to-die fabrics, and system-level co-design. As design complexity increases, engineering teams across compute, networking, AI accelerators, RF, memory, and advanced packaging are demanding faster ways to explore architectures, evaluate trade-offs, and validate system performance before any RTL or silicon investment.
At this year’s Chiplet Summit—held on February 17–19 at the Santa Clara Convention Center—Mirabilis Design will demonstrate how system architects and semiconductor designers can accelerate innovation with VisualSim Architect, the industry’s most comprehensive system-level modeling and architecture-exploration platform.
Exhibits: Booth 314- Ask for Kesudh, Pavan, Vaish or Deepak
Paper Presentations
| Deepak Shankar | MIRABILIS DESIGN | H-103: Design – 3 | Wednesday | 5:00 PM |
| Tom Jose | MIRABILIS DESIGN | A-201: Design – 4 | Thursday | 9:00 AM |
| Mohan Dhene | QUALCOMM | F-201: Die-to-Die Interfaces – 5: High-Frequency Applications | Thursday | 9:00 AM |
Forums
| Deepak Shankar | MIRABILIS DESIGN | Electronic Design Forum | Wednesday | 4:10 PM |
Below is a preview of the graphic featured at our booth. It illustrates how VisualSim Architect models Compute, GPU/AI/NPU, Analog, RF, and HBM/Memory chiplets connected through UCIe and OCP Bunch of Wires, with integrated power delivery, latency, throughput, heat, and runtime power plots—all generated from real system-level simulation.
UCIe (Universal Chiplet Interconnect Express)
Component
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