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Benefits

Using the FPGA block in VisualSim provides:

  • Cross-Vendor Support: Simulates major FPGA families from AMD-Xilinx, Intel (Altera), Microchip, and custom IP providers.
  • Hardware-Software Partitioning: Evaluate which functions run in PL vs. embedded cores.
  • Performance Optimization: Explore DMA throughput, cache usage, and AXI interconnect bottlenecks.
  • Scalability: Configure single-FPGA systems to large, multi-FPGA designs.
  • Power/Performance Trade-offs: Balance workload acceleration vs. energy efficiency.
  • System Validation: Test FPGA subsystems in context of larger SoC or system-level design.

The FPGA (Field-Programmable Gate Array) block in VisualSim models programmable logic devices that integrate custom hardware logic with embedded processing cores and AI tiles. Modern FPGAs such as AMD-Xilinx Versal, Ultrascale, and Zynq families combine programmable logic (PL) with multi-core ARM Cortex processors and AI network of engines, making them powerful platforms for high-performance computing, embedded systems, and real-time applications.

FPGAs first emerged in the 1980s, pioneered by Xilinx and Altera, as a way to give designers reconfigurable hardware without fixed-function ASIC costs. Over time, vendors such as AMD-Xilinx, Altera, and Microchip have expanded FPGA capabilities, integrating CPUs, DSPs, GPUs, and high-speed I/O. Today, FPGAs power AI acceleration, 5G, automotive ADAS, aerospace, and industrial automation, where low-latency, high-bandwidth, and customizable hardware are critical.

The FPGA block in VisualSim allows architects to evaluate application partitioning, programmable logic utilization, memory bandwidth, DMA transfers, and software-hardware partitioning. It provides system-level visibility into timing, throughput, and workload mapping across FPGA subsystems.

Overview

The FPGA block includes the following configurable features:

  • Embedded Processing Units: Multi-core ARM processors for embedded software execution.
  • High-Bandwidth Memory Controllers: DDR and OCM controllers for low-latency storage access.
  • Programmable Logic (PL) Interfaces: Support for high-speed peripherals and custom hardware logic blocks.
  • AXI Interconnects & DMA Controllers: Optimized data transfer between processors, memory, and programmable logic.
  • Interrupt & Power Management: Hardware-based features to ensure efficiency in real-time systems.
  • Configurable Fabric Utilization: Explore logic, DSP slices, and block RAM allocation.
  • Heterogeneous Acceleration: Partition workloads between CPUs, DSP engines, AI accelerators, and custom logic.

Supported Standards

While marked as “No Standards” in the original entry, the FPGA block models designs compatible with:

  • AMBA AXI / AHB / NoC Interconnects (widely used in FPGA SoCs).
  • PCIe / CXL / UCIe for chip-to-chip and chiplet interconnects.
  • Ethernet, CAN, and proprietary buses for real-time I/O.
  • IEEE 754 Floating-Point and DSP standards for compute workloads.

Key Parameters

Configurable simulation parameters include:

  • RPU_Operation_Mode: Defines operation of real-time processing units.
  • FPGA_Num: Identifies FPGA instance in multi-FPGA systems.
  • DDR_Name: Defines connected DDR/LPDDR memory type.
  • OCMRam: Configurable On-Chip Memory parameters.
  • L2_Mem: L2 cache/memory configurations.
  • Logic Utilization: % of FPGA logic fabric in use.
  • DSP/BRAM Allocation: Allocation of dedicated DSP slices and block RAM.
  • AXI Bus Bandwidth: Configurable interconnect performance.

Parameter Snapshots

  • Parameter 1

Simulation Results

  • Throughput Analysis: Effective bandwidth of DMA and interconnects.
  • Latency Studies: End-to-end execution times across PL and ARM cores.
  • Utilization Reports: Logic, DSP, and memory block usage.
  • Power/Performance Trade-offs: Impact of different workload partitioning strategies.
  • Latency
  • Plot 1
  • Plot 2
  • Plot 3
  • Stats

Application

FPGAs are used wherever programmable, parallel, and low-latency computing is needed:

  • AI/ML Acceleration: Custom inference and training engines with reduced latency.
  • 5G and Networking: Packet inspection, baseband processing, and signal acceleration.
  • Automotive ADAS: Sensor fusion, perception, and autonomous driving algorithms.
  • Aerospace & Defense: Flight control, radar, and secure communications.
  • Industrial Automation: Real-time control, robotics, and PLC acceleration.
  • Prototyping & SoC Validation: Hardware/software co-design and rapid prototyping.

Integrations

  • Works with processors, caches, and interconnect models (CoreLink, Arteris NoC).
  • Can connect with DDR/LPDDR/GDDR/Flash models for realistic memory studies.
  • Supports chiplet and die-to-die protocols (UCIe, CXL).
  • Integrates with DSP, AI, and accelerator models for heterogeneous workloads.
  • Interfaces with custom IP models, allowing exploration of third-party FPGA IP blocks.

View Demo

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