Mobile Menu

Benefits

  • Captures variability and burstiness that deterministic models ignore, leading to more realistic performance and reliability predictions.
  • Supports analysis of tail latency, deadline misses and SLA violations under real workloads.
  • Enables early resource sizing and capacity planning across cores, memory channels, links and queues.
  • Reduces risk of over- or under-provisioning by exposing bottlenecks before implementation.
  • Provides a consistent abstraction that can be reused across multiple projects and domains.

The Stochastic Resource Model library in VisualSim Architect provides a set of reusable building blocks for representing hardware, software, networking and semiconductor components as resources with probabilistic behavior. Rather than assuming fixed execution and transfer times, designers can specify delays, availability and contention using distributions and policies.

These models are used to explore the performance, reliability and power behavior of future architectures, long before RTL or software prototypes exist. A single set of resource blocks can be configured to represent processors, memories, interconnects, operating systems and device-level controllers.

Overview

This library includes fundamental resource primitives that can be combined to create complex architectures:

  • Queue – Buffers incoming transactions until a resource is available, supporting FIFO, LIFO and priority-based ordering.
  • Server – Single resource instance that processes one transaction at a time with a deterministic or stochastic service delay.
  • ServerN – A pool of N identical servers; transactions are assigned to any available instance, enabling multicore and parallel-processing models.
  • Scheduler – Allocates requests to resources based on a configurable policy such as Round Robin, static priority or EDF (Earliest Deadline First).
  • SystemResources – Models shared resources (e.g., memory banks, cores, IO channels) with configurable capacity and allocation rules.
  • SystemResources_Extend – Adds advanced features such as timeouts, dependency handling and reservation mechanisms.
  • SystemResources_Done – Marks completion of processing and returns the resource to the available pool, closing the allocation lifecycle.

Together, these blocks allow designers to build stochastic models of processors, memories, Ethernet links, RTOS schedulers and more using a consistent resource abstraction.

Supported Features

  • Support for common probability distributions:
    • Uniform, Normal, Exponential, Poisson, Pareto, Gamma
  • Queueing policies:
    • FIFO, LIFO, Static Priority, Dynamic Priority, Round Robin, EDF
  • Preemption and time-slicing for server resources.
  • Configurable timeout, retry and backoff behavior.
  • Blocking, non-blocking and asynchronous event handling.
  • Resource-state modeling for active, idle, sleep and failure modes.
  • Statistical triggers for DVFS and power-state transitions.

Key Parameters

  • Service_Time – Constant, table-based or distribution-driven execution delay.
  • Distribution_Type – Uniform, Normal, Exponential, Poisson, Pareto, etc.
  • Queue_Size – Maximum number of transactions that can be buffered.
  • Overflow_Behavior – Drop, overwrite, block or redirect to overflow port.
  • Scheduling_Policy – FIFO, LIFO, Priority, Round Robin, EDF.
  • Server_Count – Number of parallel servers in ServerN blocks.
  • Timeout – Time after which a waiting transaction is considered failed or rerouted.
  • Power_State – Power level associated with active, idle, sleep and failure states.
  • Utilization_Thresholds – Triggers for scaling resources up or down.
  • Busy / Done Flags – Interface signals for synchronization with other blocks.

Analysis and Reports

Example analysis outputs include:

  • Latency distributions with percentiles (P50, P90, P99, max latency).
  • Throughput per server, per resource pool and per end-to-end path.
  • Queue depth over time, overflow counts and starvation statistics.
  • Deadline miss ratios and SLA compliance metrics.
  • Utilization and idling patterns for each resource.
  • Correlation between workload intensity, performance and power consumption.

Applications

  • Semiconductor and SoC Architecture
    • Processor pipelines, functional units and execution clusters.
    • DDR/LPDDR/HBM memory controllers and banks.
    • On-chip interconnect and fabric arbitration (with AMBA, NoC, UCIe etc.).
  • Data Center and Networking Systems
    • Ethernet/TSN switches, routers and firewalls.
    • Queueing and scheduling for NVLink, PCIe, RoCE and custom fabrics.
    • Modeling congestion, packet drops and fairness across flows.
  • Automotive and Aerospace
    • RTOS scheduling of safety-critical and best-effort tasks.
    • ECU resource contention and gateway behavior.
    • Flight-control, radar and mission-computer workloads.
  • Embedded and IoT Systems
    • Sensor and actuator scheduling with sleep/active duty cycles.
    • Battery-powered platforms with variable workload intensity.
  • Software Performance Modeling
    • Thread pools and microservice request handling.
    • Message queues and inter-process communication (IPC).

Integrations

The Stochastic Resource Model library integrates with:

  • VisualSim processor, cache and memory libraries for multicore and heterogeneous SoCs.
  • AMBA, PCIe, UCIe, Corelink and Arteris NoC components for complete interconnect modeling.
  • Power-management models for DVFS, clock gating, active/idle/sleep state transitions.
  • Traffic generators and trace-based workloads for realistic system-level test scenarios.
  • Visualization, reporting and design-space exploration scripts in VisualSim.

Schedule a consultation with our experts

    Subscribe