Component:Test and Verification

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Benefits

Ensures implementation matches architectural specification — eliminates ambiguity
Enables early test automation before RTL or software is complete
Supports timing, power and behavior verification using the same model
Reduces debug time and verification iterations
Preserves a reference “golden model” for all future tests and corner cases
Simplifies downstream coverage and compliance validation

The Test and Verification library in VisualSim Architect enables users to validate that the hardware, software and system implementation matches the original architectural specification. It supports both offline and online verification, including replay-style testing, co-simulation, and live validation on emulators or real targets.

This library bridges system-level models and implementation platforms by providing standardized interfaces for traffic, stimulus, events, interrupts, software sequencing, and timing-accurate checks. The goal is to ensure functional correctness, timing, power, and behavior fidelity between the model and the actual implementation.

Overview

The Test and Verification library provides multiple ways to connect VisualSim models to implementation environments:

VCD-based trace replay for generating identical traffic patterns and comparing output and statistics
C-code / software execution with variable input conditions and dynamic event ordering
Co-simulation with RTL / HDL simulators via standard interfaces
Emulator and FPGA board testing using live network or PCIe-style system traffic
ECU / onboard computer validation via network streams for automotive and aerospace systems

Users can run thousands of automatic tests using different input profiles, rates, arbitration selections, control paths, scheduling tables, and power-state sequences — all against a single, reusable VisualSim reference model.

Key Parameters

Test_Mode — replay, co-sim, live traffic or software-driven
Stimulus_Source — VCD, C-code, network packet stream, API-driven, power-state triggers
Input_Profile — traffic pattern, data rate, arbitration path, event timing
Software_Execution_Sequence — task order, interrupts, priority levels
Expected_Output — functional values, timing windows, statistical scoreboard
Pass/Fail_Criteria — tolerances for timing, power, throughput and logic correctness
Reference_Trace_Format — VCD, CSV, binary trace, JSON, custom
Regression_Iteration_Count — number of tests per run / variation space
Coverage_Targets — logic, schedule path, bandwidth, traffic, power-state coverage
Control_Hooks — external stop / sync / checkpoint / callback

Analysis and Reports

Functional correctness (bit-/value-level)
Scheduling and event-order correctness
Deadline hit/miss and throughput deviation
Power and energy deviation vs. reference
Scorecards of arbitration / flow selection consistency
Coverage and regression summary for thousands of tests
Implementation-vs-reference waveform / trace deviation reports

Applications

Silicon and IP bring-up validation
C, C++, firmware and bare-metal software verification
RTOS scheduling and event priority regression testing
Network / interconnect / NoC behavior reproduction and comparison
Automotive / aerospace ECU / onboard computer HIL-style verification
Power-aware and performance-aware compliance testing
Generating test specification for downstream verification teams

Integrations

Traffic generators and VCD / trace interfaces
RTL simulators, emulators and FPGA prototype links
C-model interaction and software API integration
Scheduling / RTOS models for software-execution-path testing
Power and Thermal libraries for cross-domain timing-power verification
Communication System and ECU / onboard-compute interfaces for hardware-in-loop style testing