ARM Cortex A53 Processor System

This model shows VisualSim’s Cortex A53 implementation by simulating a network application task profile provided
by NpBench. As soon as the model opens click on the RUN button (Green) in the toolbar at the top. You will see a
bunch of windows opening. These windows show the results obtained from the simulation such as Task Latency,
Task Set Latency, Power Consumption, and Statistics of the components of the model.

For further exploration of the model:
1) Double-Click on any block to get the specifications and parameters used for the block.
2)Some blocks, called hierarchical blocks, contain components within them. To see the working of a hierarchical block,
Right-Click on the block and select “Open Block”. The hierarchical blocks present in this model are “Task Generator” and “Plots”

—————————————Cortex A53 Model—————————————

The Processor is also connected to an external Cache and DRAM via a bus. These are memory blocks were the processor gets
data from when a miss occurs within internal cache. It also has DMA connected, which will give the processor the power to
access the DRAM directly.