Mobile Menu
← Back to Board and System Interfaces

PCI/PCIx

Demonstrates the use of PCI to handle the arbitration between multiple requesters and memory

PCI_Bus_Model

Browsable image of the model.

  • To download OpenWebStart click on the links –
    Windows– Compatibility:Windows 10 or higher (*)
    macOS – Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux – Compatibility:Ubuntu 18.04 LTS or higher (*)
Launch
  • Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
<h2>Traffic2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>100.0E-9</td><td>1.0E-7</td></tr><tr><td>Value_1</td><td>1.0E-06/IO_Speed_Mhz</td><td>1.0E-6</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Single Event</td><td>Single Event</td></tr></table> <h2>Traffic4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>100.0E-9</td><td>1.0E-7</td></tr><tr><td>Value_1</td><td>1.0E-06/IO_Speed_Mhz</td><td>1.0E-6</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Single Event</td><td>Single Event</td></tr></table> <h2>Traffic3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>1.0E-06/IO_Speed_Mhz</td><td>1.0E-6</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Single Event</td><td>Single Event</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Bytes = 100\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 2\\ninput.A_Command = &quot;Write&quot;</td><td>input.A_Bytes = 100\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 2\\ninput.A_Command = &quot;Write&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Bytes = 100\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 2\\ninput.A_Command = &quot;Write&quot;</td><td>input.A_Bytes = 100\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 2\\ninput.A_Command = &quot;Write&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Bytes = 128\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 0\\ninput.A_Command = &quot;Write&quot;</td><td>input.A_Bytes = 128\\ninput.A_Bytes_Remaining = 0\\ninput.A_Priority = 0\\ninput.A_Command = &quot;Write&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Detailed Processor Activity&quot;</td><td>&quot;Detailed Processor Activity&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>DeviceInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_2&quot;</td><td>&quot;IO_2&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>IO_Command</td><td>&quot;A_Command&quot;</td><td>&quot;A_Command&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Timing_Diagram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Proc_Name</td><td>&quot;Processor_1&quot;</td><td>&quot;Processor_1&quot;</td></tr><tr><td>Bus_Name</td><td>Bus_Name</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_1&quot;</td><td>&quot;Cache_1&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>AXI_Name</td><td>&quot;AXI_1&quot;</td><td>&quot;AXI_1&quot;</td></tr><tr><td>Memory_Controller_Name</td><td>&quot;LPDDR_1&quot;</td><td>&quot;LPDDR_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>_explanation</td><td>Hardware Setup-&gt;Timing_Diagram</td><td>Hardware Setup-&gt;Timing_Diagram</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-6</td></tr></table> <h2>PCI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>Bus_Name</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>33.0</td><td>33.0</td></tr><tr><td>Bus_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>Burst_Size_Bytes</td><td>32</td></tr><tr><td>FIFO_Buffers_Size</td><td>FIFO_Buffers_Size</td><td>8</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCI_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCI_Bus</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-6</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */</td><td>/* First row contains Column Names. */</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>33.0</td><td>33.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 30.0, Prefetch 6.0, Write 30.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 30.0, Prefetch 6.0, Write 30.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>16</td><td>16</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>DDR2</td><td>DDR2</td></tr></table> <h2>DeviceInterface3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_3&quot;</td><td>&quot;IO_3&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>IO_Command</td><td>&quot;A_Command&quot;</td><td>&quot;A_Command&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>DeviceInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_1&quot;</td><td>&quot;IO_1&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>IO_Command</td><td>&quot;A_Command&quot;</td><td>&quot;A_Command&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table>

“The PCI bus block can be use as interconnect between high bandwidth peripherals closer to the CPU for performance gains. This model has been fully validated against the specification. This library component is used to assemble complex systems that contain one or more PCI buses. The PCI provides split-and-retry, First Come-First Server and Round-Robin arbitration.

Preemption: The PCI and PCIx will preempt at the transaction level and not at the burst-level. If the user would like to preempt at the burst-level, the transaction must be fragmented into bursts before being sent into the PCI /PCIx Bus block. At the destination side (Slave), the bursts must be assembled before presenting to the Slave device. This can be done by testing for the A_Bytes_Remaining field to be equal to 0.

    Contact Us

    Subscribe