Browsable image of the model.
Demonstrates the use of the Traffic block to generate transactions based on multiple districtions
Generating Ethernet traffic based on traffic profile
Generate images in the form of a Matrix for processing
Mapping SysML to a performance analysis model for Model-based System Simulation
Use of the Queue block to model the buffer management, ingress/egress queues, FIFO and SRAM in FPGAs
Use of the Server block to model time-consumption by system resources. Resources can include hardware, RTOS, middleware, networks and interrupts
Mapping an MPEG use case to SystemResources for performance and power analysis
Modeling consumption of quantity which can be memory addresses, semaphore pool and slots avaialable in a parking garage
Use of the Channel block to model communication, wireless and interface channels
The design of automotive architectures has become a complex and time consuming process with automotive designers spending more time on the modeling infrastructure and less time on creating innovative products. Concurrent interactions between Electronic Control Units (ECU’s) and the communications network can cloud overall analysis of an entire system. For many years it has been relatively easy to add the necessary system level details to get better results. Standardizing common modeling elements, such as the AUTomotive Open System Architecture (AUTOSAR) – Virtual Functional Bus (VFB1), has been a positive step towards adding complex components. This paper takes the AUTOSAR VFB one step further from the perspective of abstracting essential system details into Spreadsheets. It comprises the logic and flow of the modeling components to speed up model construction while retaining accuracy. Readers not familiar with the AUTOSAR methodology can refer to the first web reference for more background information.
This methodology could be extended to ECU’s and other components to provide designers with the ability to plug-n-play different topologies using spreadsheets as the primary model input. Software can be contained in C code graphical blocks at the model level, triggering Internal Modeling Blocks. It captures Communication Network Topology, Resource Utilization, Timing Latency, Power, etc. that reflect the AUTOSAR VFB components. Making a model simpler involves deleting what is not essential information? and looking at the entire modeling infrastructure to see what information is essential to obtain accurate results for:
Allocation of ECU functions
Communication bandwidths
Timing constraints
Reliability considerations
This paper will examine such a methodology, where it will take only one spreadsheet cell to process a transaction on a bus, or ECU processing element. Additional spreadsheet cells provide the necessary logic and expressions only when needed. Separate resource spreadsheets make it easier to maintain and modify the overall configuration. As a result, automotive designers will be able to spend more time on a new design, less time on the modeling infrastructure and create higher quality products.
Demonstrates the use of the Traffic block to generate transactions based on multiple districtions
Generating Ethernet traffic based on traffic profile
Generate images in the form of a Matrix for processing
Mapping SysML to a performance analysis model for Model-based System Simulation
Use of the Queue block to model the buffer management, ingress/egress queues, FIFO and SRAM in FPGAs
Use of the Server block to model time-consumption by system resources. Resources can include hardware, RTOS, middleware, networks and interrupts
Mapping an MPEG use case to SystemResources for performance and power analysis
Modeling consumption of quantity which can be memory addresses, semaphore pool and slots avaialable in a parking garage
Use of the Channel block to model communication, wireless and interface channels