Xilinx Ultrascale

“This models demonstrates the use of VisualSim in exploring the buffering requirements and the clock speeds of the hardware platform for a target packet flow. In addition, the written task is sent to a QuadCore ARM Cortex A53 on the Xilinx Ultrscale platform. The cores are connected using the AMBA AXI bus to DDR memory controller. The hardware model is used to evaluated the processing requirements of the data stream.

In this model, the data is arriving at a fixed rate of 60hz and the size is 512 pixels per line with 24 bit pixels and 1024 lines. Each line is written to Bus and then the DRAM. When a line is written to the DDR4, an interrupt is sent to the processor core using the Switch block. The lines are sent in a Round-Robin to the cores from 0-3. When each core has finished the task processing, the next line waiting in the queue is processed. The completed transaction is sent to the plotter to display the latency.

When half the lines (512) have been written, the Egress starts reading the data out of the DRAM.The time of completion of each line is plotted. Statistics are generated for the bus and the DRAM. The DRAM Controller emulates the controller latency associated with sequential and random accesses. As all the requests are arriving at the exact same time (60hz), it is hard to attain maximum utilization.

The flow works as follows:

• Traffic triggers the input every 60hz; ExpressionList updates the transaction with informati

on on the transaction

• Script block generates the lines; Mapper feeds the requests + data to the Bus
• The Bus or SystemResource delays for the bus and sends to the DRAM.
• The DRAM controller determines the Controller delay based on sequential and random/ read vs write. The RAM block delays the controller (first word) and the array access.
• When the line has been fully written to the DRAM, an interrupt is sent to the switch. The switch maintains a modulo counter to 3 and sends the sequence of lines to the cores in a Round-Robin fashion. When the task is done, the next line is processed. The processor is kept continuously busy.
• The cores are A53 and connected to the AXI and DDR4 memory.
• The task on the processor uses an instructiuon sequence that emulates the NP Benchmark. The instructions are generated based on the profile provided to the Task_Generator block.
• When half (512) lines have been written, the second part ExpressionList+Script generates read request which are sent by the second Mapper to the Bus,
• The Mapper is non blocking and will send the transaction out to the DRAM when it has been transfered across the Bus.”