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ARM AMBA AHB/APB

Shows a network containing a AHB connected to an AXI bus via bridge.

AHB_AXI_Bus

Browsable image of the model.

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<h2>DS_xTime_yData_Plotter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>Field_Trace_Name</td><td>Plot_Name</td><td>&quot;Plot_Name&quot;</td></tr><tr><td>Field_Y_Value</td><td>input.Plot_Value</td><td>&quot;input.Plot_Value&quot;</td></tr><tr><td>Field_Color</td><td>Plot_Color</td><td>&quot;Plot_Color&quot;</td></tr><tr><td>Field_Offset</td><td>Plot_Offset</td><td>&quot;Plot_Offset&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>TextDisplay2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\n/*Result_A = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_2&quot;, &quot;output2&quot;)\\nResult_B = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM3&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_2&quot;, &quot;output2&quot;)\\nResult_C = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM&quot;,&quot;output&quot;,&quot;AHB_Bus_2_Port_8&quot;, &quot;output2&quot;)\\nResult_D = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM3&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_8&quot;, &quot;output2&quot;)*/</td><td>/* Template to enter multiple RegEx lines*/\\n/*Result_A = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_2&quot;, &quot;output2&quot;)\\nResult_B = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM3&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_2&quot;, &quot;output2&quot;)\\nResult_C = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM&quot;,&quot;output&quot;,&quot;AHB_Bus_2_Port_8&quot;, &quot;output2&quot;)\\nResult_D = addDeviceToBus(&quot;Architecture_1&quot;, &quot;DDRDRAM3&quot;,&quot;output&quot;,&quot;AHB_Bus_1_Port_8&quot;, &quot;output2&quot;)*/</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>getRoutingTable(&quot;Architecture_1&quot;)</td><td>&quot;getRoutingTable(&quot;Architecture_1&quot;)&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Destination = &quot;MAC_ARM9&quot;\\ninput.A_Hop = &quot;MAC_ARM9&quot;\\ninput.TIME = TNow\\ninput.INDEX = 1</td><td>input.A_Destination = &quot;MAC_ARM9&quot;\\ninput.A_Hop = &quot;MAC_ARM9&quot;\\ninput.TIME = TNow\\ninput.INDEX = 1</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TriggeredTraffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Timing_Diagram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Proc_Name</td><td>&quot;MAC_ARM9&quot;</td><td>&quot;MAC_ARM9&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_2&quot;</td><td>&quot;AHB_Bus_2&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>AXI_Name</td><td>&quot;AXI_Level_2&quot;</td><td>&quot;AXI_Level_2&quot;</td></tr><tr><td>Memory_Controller_Name</td><td>&quot;LPDDR_1&quot;</td><td>&quot;LPDDR_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>_explanation</td><td>Hardware Setup-&gt;Timing_Diagram</td><td>Hardware Setup-&gt;Timing_Diagram</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr></table> <h2>Database2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\nMy_Task_1\t LD_LDR\t 0\t DDRDRAM2\t 32\t 1 Write 256\t0\t DMA \\nMy_Task_2\t LD_LDR\t 0\t DDRDRAM2\t 32\t 1 Write\t128\t1\t DMA \\nMy_Task_3\t LD_LDR\t 0\t DDRDRAM2\t 32\t 2 Write\t128\t3\t DMA \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\nMy_Task_1\t LD_LDR\t 0\t DDRDRAM2\t 32\t 1 Write 256\t0\t DMA \\nMy_Task_2\t LD_LDR\t 0\t DDRDRAM2\t 32\t 1 Write\t128\t1\t DMA \\nMy_Task_3\t LD_LDR\t 0\t DDRDRAM2\t 32\t 2 Write\t128\t3\t DMA \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>Bridge</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge&quot;</td><td>&quot;Bridge&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>SingleEvent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_explanation</td><td>Source-&gt;Event-&gt;SingleEvent\t</td><td>Source-&gt;Event-&gt;SingleEvent\t</td></tr><tr><td>time</td><td>1.0e-9</td><td>1.0E-9</td></tr><tr><td>value</td><td>true</td><td>true</td></tr></table> <h2>DRAM5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM1&quot;</td><td>&quot;DRAM1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr><tr><td>Refresh</td><td>false</td><td>false</td></tr></table> <h2>AMBA_AHB2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_2&quot;</td><td>&quot;AHB_Bus_2&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_2_Port_1&quot;, &quot;AHB_Bus_2_Port_2&quot;, &quot;AHB_Bus_2_Port_3&quot;, &quot;AHB_Bus_2_Port_4&quot;, &quot;AHB_Bus_2_Port_5&quot;, &quot;AHB_Bus_2_Port_6&quot;, &quot;AHB_Bus_2_Port_7&quot;, &quot;AHB_Bus_2_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;DDRDRAM&quot;,&quot;DDRDRAM2&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;DDRDRAM&quot;, &quot;DDRDRAM2&quot;}}</td></tr></table> <h2>Bridge2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge2&quot;</td><td>&quot;Bridge2&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>AMBA_AHB</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_1&quot;</td><td>&quot;AHB_Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_1_Port_1&quot;, &quot;AHB_Bus_1_Port_2&quot;, &quot;AHB_Bus_1_Port_3&quot;, &quot;AHB_Bus_1_Port_4&quot;, &quot;AHB_Bus_1_Port_5&quot;, &quot;AHB_Bus_1_Port_6&quot;, &quot;AHB_Bus_1_Port_7&quot;, &quot;AHB_Bus_1_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;DDRDRAM&quot;,&quot;DDRDRAM2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;DDRDRAM&quot;, &quot;DDRDRAM2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>AMBA_AXI4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_Level_2&quot;</td><td>&quot;AXI_Level_2&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>6.0240963855422E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>8</td><td>8</td></tr><tr><td>Write_Threshold</td><td>8</td><td>8</td></tr><tr><td>Master_Request_Threshold</td><td>{4,2,2,4,2,2,2,2} </td><td>{4, 2, 2, 4, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>2</td><td>2</td></tr><tr><td>Number_Slaves</td><td>3</td><td>3</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>true</td><td>true</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{166.0, 166.0, 166.0, 166.0, 166.0, 166.0, 166.0, 166.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DDRDRAM&quot;},{&quot;DDRDRAM2&quot;},{&quot;DDRDRAM3&quot;},{&quot;Device_4&quot;}}</td><td>{{&quot;DDRDRAM&quot;}, {&quot;DDRDRAM2&quot;}, {&quot;DDRDRAM3&quot;}, {&quot;Device_4&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,true,true,true,true,true,true}</td><td>{false, false, true, true, true, true, true, true}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false} </td><td>{false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{1,2} /* master n, slave m, 0 disables */</td><td>{1, 2}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr></table> <h2>uProcessor2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed</td><td>100.0</td></tr><tr><td>Rate_in_Cycles</td><td>256.0</td><td>256.0</td></tr><tr><td>Bus_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>Bus_Transaction_Size_Bytes</td><td>32</td><td>32</td></tr><tr><td>Master_Source</td><td>&quot;uProcessor2&quot;</td><td>&quot;uProcessor2&quot;</td></tr><tr><td>Master_Destination</td><td>&quot;DRAM1&quot;</td><td>&quot;DRAM1&quot;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr></table> <h2>uProcessor</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed</td><td>100.0</td></tr><tr><td>Rate_in_Cycles</td><td>256.0</td><td>256.0</td></tr><tr><td>Bus_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>Bus_Transaction_Size_Bytes</td><td>32</td><td>32</td></tr><tr><td>Master_Source</td><td>&quot;uProcessor&quot;</td><td>&quot;uProcessor&quot;</td></tr><tr><td>Master_Destination</td><td>&quot;DDRDRAM3&quot;</td><td>&quot;DDRDRAM3&quot;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr></table> <h2>DRAM4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DDRDRAM3&quot;</td><td>&quot;DDRDRAM3&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr><tr><td>Refresh</td><td>false</td><td>false</td></tr></table> <h2>DRAM3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>aEnter User Documentation Here</td><td>aEnter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DDRDRAM2&quot;</td><td>&quot;DDRDRAM2&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;0.0&quot;</td><td>&quot;0.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr><tr><td>Refresh</td><td>false</td><td>false</td></tr></table> <h2>DRAM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DDRDRAM&quot;</td><td>&quot;DDRDRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;0.0&quot;</td><td>&quot;0.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr><tr><td>Refresh</td><td>false</td><td>false</td></tr></table> <h2>Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>Miss_Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Cache_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Cache_Size_KBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Words_per_Cache_Line</td><td>16</td><td>16</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Cache_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td></tr><tr><td>Cache_Hit_Expression</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>10</td><td>&quot;10&quot;</td></tr><tr><td>Speed_Mhz</td><td>Bus_Speed</td><td>&quot;Bus_Speed&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC ; /* one execution unit */\\n EXEC INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n #LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC ; /* one execution unit */\\n EXEC INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n #LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>SoftGen</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;My_SoftGen&quot;</td><td>&quot;My_SoftGen&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Loop&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Loop&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>5.0E-4</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table.txt</td><td>&quot;Instruction_Mix_Table.txt&quot;</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>166.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td><td>&quot;Read 3.0, Prefetch 3.0, Write 3.0, ReadWrite 3.0, Erase 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr><tr><td>Refresh</td><td>false</td><td>false</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\n</td><td>/* First row contains Column Names. */\\n</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean&quot;</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Bus</td><td>Bus</td></tr></table> <h2>ARM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;MAC_ARM9&quot;</td><td>&quot;MAC_ARM9&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed\\nContext_Switch_Cycles: 200 /* switch between internal pipeline stages */\\nInstruction_Queue_Length: 3 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages: 5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units: 1 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units: 0 /* no particular FP units */\\nMemory_Database_Reference: DMADatabase\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=I_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache} \\nD_1: {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=D_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache} </td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed\\nContext_Switch_Cycles: 200 /* switch between internal pipeline stages */\\nInstruction_Queue_Length: 3 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages: 5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units: 1 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units: 0 /* no particular FP units */\\nMemory_Database_Reference: DMADatabase\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=I_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache} \\nD_1: {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=D_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache} </td></tr><tr><td>Pipeline_Stages</td><td>/* Pipeline stages in ARM */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_DECODE I_1 wait none ; /* Decode */\\n3_EXECUTE ARM exec none ; /* Execute ARM instr */\\n4_MEMORY ARM wait none ; /* Wait for ARM instr */\\n4_MEMORY D_1 write none ; /* Write */\\n4_MEMORY D_1 read none ; /* Read */\\n5_WRITE_BACK D_1 wait none ; /* Wait for Mem transaction */</td><td>/* Pipeline stages in ARM */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_DECODE I_1 wait none ; /* Decode */\\n3_EXECUTE ARM exec none ; /* Execute ARM instr */\\n4_MEMORY ARM wait none ; /* Wait for ARM instr */\\n4_MEMORY D_1 write none ; /* Write */\\n4_MEMORY D_1 read none ; /* Read */\\n5_WRITE_BACK D_1 wait none ; /* Wait for Mem transaction */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table>

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