Display Systems

The Video Processing Front End creates new images based on top level parameters in the model:

(1) X_Pixels
(2) Y_Pixels
(3) Color_Bits
(4) Raw_Enabled

The last parameter sets a field of the image data structure, called A_Raw_Image to true or false. The first three determine the image size in Bytes by the Image_Bytes parameter:

(X_Pixels*Y_Pixels*Color_Bits)/8

This precalulates the image size, which is then placed in the Image_Sensor data structure. The image arrives at the CCDC hierarchical block. Inside the CCDC hierarchical block it sends a message via the 32 bit configuration bus that an image has arrived. The 32 bit configuration bus then sends the message to the RTOS block, which in turn executes a control CCDC task on the ARM processor. The control task is generated in the Instruction_Mix_Table from the SoftGen. When this control task completes on the ARM, it returns to the RTOS block, which then sends register updates to the CCDC block, and processes the incoming image.

There is a delay for the register updates, then the image is processed in the CCDC block, based on the Image_Bytes value:

Cycle_Time*(Image_Bytes/Width_Bytes)

where cycle time is clock period of the CCDC block. This block also keeps track of how many times the H3A image has been sampled by a value set in the InitMemory block. If the field Sample_Count is incremented and if the Sample_Max (InitMemory value) is reached, then Sample_Count is set to zero. The CCDC blocks sends the image to the buffer, H3A and iPipe blocks.

Inside the Buffer, connected to the 64 bit bus, the request is fragmented into 64 byte write bursts and sent to the SDRAM_1. Inside the H3A and iPipe blocks, there is processing of the CCDC image, based on the conditions. The image arriving at the H3A sends a message to the RTOS, like the CCDC, indicating an image has arrived ready to be processed. Similarly, the image arrives at the iPipe and sends a message to the RTOS via the configuration bus.

If the H3A Sample_Count field of the arriving data structure is 0, signifying that this image should be processed, it will set the processing delay to a positive value, else it will set it to zero. Like CCDC block, the H3A block waits for the ARM processor to send a message to start processing. Once this message is received, it models the register update time, and the processing time. The processing time can be 0.0 for a non-sampled image. In addition, if the processing time in the field DELTA is 0.0, nothing will be sent to the buffer.

The iPipe will also wait for the ARM control task to complete before it performs it’s processing. Currently, there is no logic for the type of processing the iPipe will perform. It could perform a raw to YCbCr conversion, subtract a dark frame, or send to SDRAM_1, for example. For now, we just use a simple delay.

Once, all of the 1/30 sec image has been processed one can calculate the time margin (positive value) or time deficit (negative value) of the original image:
Delta = TNow – input.TIME
Frame_Delay = “Frame_Delay = ” + (Frame_Time – Delta)
where Frame_Time will be 1 / 30 of a second, input.TIME is the original image time, TNow is the current simulation time.

The ARM processor is a 926. The cache size and clock speed can be modified. The processor gets the instruction and data from the SDRAm, connected to the 64-bit Bus.

The DMA is added to the 32-bit and the 64-bit Buses. This model is currently not using the DMA.

The 32-bit bus is used to communicate between the CCDC, H3A and the iPIPE with the ARM. The 64-bit bus is used to communicate between the Buffer logic and the SDRAm; and the ARM and the SDRAM.

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