Modeling a video streaming server that is stored on a redundant NAS
SSD using a generic Flash and a RISC-V for processing
Evaluate flash from different memory vendors by varying standard Flash parameters
Multi-level drive with cache, SDRAM, flash and disk drive. Uses a ARM R8 for contorl processing
Host computer with SATA interface to a local disk drive
Modeling multiple requester with addresses to DDR and LPDDR
Use of the Cache block as the L2 cache, receiving request from the I_1 and D_1 in the processor and a miss to a DRAM.
Shows an end-to-end operation with Processor core as a trace, 2 level cache, AXI bus, Memory Controller and DRAM
Modeling the cycle-accurate cache with 4-way associativity and snoop flag disabled.
