VisualSim Architect | Mirabilis Design

A general purpose, modeling and simulation software application that can be used to build graphical models, run simulations and generate reports.

VisualSim Architect is the flagship product from Mirabilis Design. This platform is used to explore the architecture of a variety of systems- semiconductor, digital, software, analog, imaging, signal processing, control systems and networks.

Systems engineers, architects, designers and verification engineers can explore and validate the specification, generate tests for the implementation, and validate the final product by integrating C or RTL code, attaching instruments and running a hardware-in-the-loop (HiL) simulation.

The product suite identifies unseen problem areas in the design process, offering users the ability to try out various combination of the attributes, and trade-off power-performance-functionality to deliver an optimized product.

VisualSim enables multiple modeling methodologies. The user can select the one that is most suitable for their exploration and application. Examples of methodologies used include the Y-chart, use cases to architecture mapping, network flow modeling and hardware-software partitioning.

Key Features

Graphical Development

Consists of four model construction options, which provide flexibility to implement their preferred methodology - Block Diagram, Finite State Machine, Script Editor and Programming

Multi-Domain

Model of computation (Link below) - Discrete-event, Synchronous Dataflow, Continuous Time, Finite State Machine and SystemC.

Modeling Library

Large library of basic modeling components including traffic generators, file readers and writers, variable and parameter management, math operators, algorithms, plotters, displays and queues.

Hierarchical

Classes and Dynamic Instantiation - Block diagrams, code, script and the FSM can be built as independent blocks and assembled hierarchically. Changes to the independent blocks will immediately update any model referencing them.

XML Database

Uses an open DTD and can easily import/export from other tools such as SysML using a custom script. Files sizes are small because they are referencing other XML files and are use-readable. Only changes specific to this instance are recorded in this model file.

Debugging Platform

Graphical debugging with animation of model execution, listeners, visual reporting of buffer usage and utilization, breakpoints, checkpoints to store intermediate model states

Report Generator

Provides over 500 user-configuration reports for latency, throughput, utilization, buffer occupancy, number exited/entered, power consumed, peak power, power/device, power/task, cumulative power, hit-miss ratio, stall time and quality-of-service.

Run-Time Simulator

License to run Monte-Carlo simulation using a command-line script. This is very useful in running a large number of parameter sweeps concurrently, distributed across multiple cores, and on a server farm.

Technology IP

Standard libraries of hardware components such as processors, memories, caches, buses, interfaces, DMA, networks, software tasks, and RTOS. These Technology IPs are integrated with the VisualSim Architect Block Diagram Editor. Technology IP are the primary reason models can be constructed so quickly.

Interfaces

Interfaces are integrated into the core of VisualSim simulator. The supported interfaces include trace files, text file import/export, datagram for interfacing with hardware, instruments and FPGA boards, SystemC, MatLab/Simulink, C/C++/Java/Python code and other XML interfaces.

Infrastructure

Enables models to be distributed across the entire network. VisualSim is platform-independent, requires less than 1 GB of disk space and about 2 GB of RAM. A large-scale model is about 3 MB in size.

Model Size and Simulator Speed

VisualSim enables models with 300 hierarchical levels to be constructed. The simulator is the fastest in the industry.