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Cache/Memory Hierarchy

Shows an end-to-end operation with Processor core as a trace, 2 level cache, AXI bus, Memory Controller and DRAM

SW_I1D1_AXI_HWDRAM

Browsable image of the model.

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<h2>TextDisplay2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Debug&quot;</td><td>&quot;Debug&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\nResult_C = addDeviceToBus(Architecture_Name, &quot;MM&quot;, &quot;MM&quot;, &quot;Bus_1_Port_1&quot;, &quot;output1&quot;)\\nResult_C = addDeviceToBus(Architecture_Name, &quot;MM2&quot;, &quot;MM2&quot;, &quot;Bus_1_Port_1&quot;, &quot;output1&quot;)\\n\\nResult_C = addToRoutingTable(Architecture_Name, &quot;Switch&quot;, &quot;MM2&quot;, &quot;D1_Cache&quot;, &quot;output&quot;)\\nResult_C = addToRoutingTable(Architecture_Name, &quot;Switch&quot;, &quot;MM&quot;, &quot;I1_Cache&quot;, &quot;output&quot;)\\n\\nResult_D = getRoutingTable(Architecture_Name)\\n</td><td>/* Template to enter multiple RegEx lines*/\\nResult_C = addDeviceToBus(Architecture_Name, &quot;MM&quot;, &quot;MM&quot;, &quot;Bus_1_Port_1&quot;, &quot;output1&quot;)\\nResult_C = addDeviceToBus(Architecture_Name, &quot;MM2&quot;, &quot;MM2&quot;, &quot;Bus_1_Port_1&quot;, &quot;output1&quot;)\\n\\nResult_C = addToRoutingTable(Architecture_Name, &quot;Switch&quot;, &quot;MM2&quot;, &quot;D1_Cache&quot;, &quot;output&quot;)\\nResult_C = addToRoutingTable(Architecture_Name, &quot;Switch&quot;, &quot;MM&quot;, &quot;I1_Cache&quot;, &quot;output&quot;)\\n\\nResult_D = getRoutingTable(Architecture_Name)\\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>Result_D</td><td>&quot;Result_D&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Transactions Complete&quot;</td><td>&quot;Transactions Complete&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>Latency_Throughput_Plots2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Traffic_Generator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Input_File</td><td>Input_File</td><td>&quot;cache_log.txt&quot;</td></tr></table> <h2>AMBA_AXI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_Right_Side&quot;</td><td>&quot;AXI_Right_Side&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>Bus_Speed</td><td>400.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / Bus_Speed</td><td>2.5E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>10</td><td>10</td></tr><tr><td>Write_Threshold</td><td>10</td><td>10</td></tr><tr><td>Master_Request_Threshold</td><td>{10,10,10,10,10,10,10,10} </td><td>{10, 10, 10, 10, 10, 10, 10, 10}</td></tr><tr><td>Number_Masters</td><td>1</td><td>1</td></tr><tr><td>Number_Slaves</td><td>2</td><td>2</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>true</td><td>true</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>2</td><td>2</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{Bus_Speed, Bus_Speed, Bus_Speed, Bus_Speed,Bus_Speed, Bus_Speed, Bus_Speed, Bus_Speed}</td><td>{400.0, 400.0, 400.0, 400.0, 400.0, 400.0, 400.0, 400.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;SDRAM&quot;},{&quot;NOR&quot;},{&quot;none&quot;},{&quot;none&quot;}}</td><td>{{&quot;SDRAM&quot;}, {&quot;NOR&quot;}, {&quot;none&quot;}, {&quot;none&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Master_Throttle_Enable</td><td>{true,true,true,true,true,true,false,false}</td><td>{true, true, true, true, true, true, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{true,true,true,true} </td><td>{true, true, true, true}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr></table> <h2>HW_DRAM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;NOR&quot;</td><td>&quot;NOR&quot;</td></tr><tr><td>HW_DRAM_Speed_Mhz</td><td>Bus_Speed</td><td>400.0</td></tr><tr><td>Number_of_Banks</td><td>8</td><td>8</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td></tr><tr><td>Memory_Width_Bytes</td><td>2</td><td>2</td></tr><tr><td>Burst_Length</td><td>BL /* 2, 4, 8 */</td><td>8</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Mfg_Suggest_Timing</td><td>Mfg_Suggest_Timing</td><td>{0, 8, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>Extra_Timing</td><td>{1, 3, 4, 6, 6, 3, 2, 3, 3}</td></tr><tr><td>Fix_DQSS</td><td>true</td><td>true</td></tr><tr><td>Refresh_Rate_per_Bank_ms</td><td>64.0 /* 64.0 ms */</td><td>64.0</td></tr><tr><td>Refresh_Cycles_per_Bank</td><td>256 /* 256 cycles per bank */</td><td>256</td></tr><tr><td>Enable_External_Data</td><td>false</td><td>false</td></tr><tr><td>Address_Bit_Map</td><td>{{0,9},{10,24},{25,27}} /* col, row, bank (min, max) Bit Position */</td><td>{{0, 9}, {10, 24}, {25, 27}}</td></tr><tr><td>Standard_Name</td><td>&quot;none&quot; /*reads DDR_Memory_Standards.txt */</td><td>&quot;none&quot;</td></tr><tr><td>Standard_File</td><td>VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt</td><td>&quot;VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Memory_Controller</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Bank_at_a_Time</td><td>true /* false=all */</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>MC2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Controller_Name</td><td>&quot;LPDDR2&quot;</td><td>&quot;LPDDR2&quot;</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Controller_Speed_Mhz</td><td>Bus_Speed</td><td>400.0</td></tr><tr><td>Memory_Width_Bytes</td><td>2</td><td>2</td></tr><tr><td>Bus_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Command_Buffer_Length</td><td>16</td><td>16</td></tr><tr><td>Commands_in_a_Row</td><td>16</td><td>16</td></tr><tr><td>Mfg_Suggest_Timing</td><td>Mfg_Suggest_Timing</td><td>{0, 8, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>Extra_Timing</td><td>{1, 3, 4, 6, 6, 3, 2, 3, 3}</td></tr><tr><td>Burst_Length</td><td>BL /* 2, 4, 8 */</td><td>8</td></tr><tr><td>Memory_Column</td><td>{0,12}</td><td>{0, 12}</td></tr><tr><td>Memory_Row</td><td>{13,25}</td><td>{13, 25}</td></tr><tr><td>Memory_Bank</td><td>{26,28}</td><td>{26, 28}</td></tr><tr><td>Memory_Bank_Length</td><td>round(pow(2,(Memory_Bank(1) - Memory_Bank(0) + 1)))</td><td>8L</td></tr><tr><td>DRAM_Return_Cycles</td><td>0</td><td>0</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR0&quot;</td><td>&quot;DDR0&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Input_Device_Name</td><td>&quot;Bus_2&quot;</td><td>&quot;Bus_2&quot;</td></tr></table> <h2>HW_DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>HW_DRAM_Speed_Mhz</td><td>Bus_Speed</td><td>400.0</td></tr><tr><td>Number_of_Banks</td><td>8</td><td>8</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td></tr><tr><td>Memory_Width_Bytes</td><td>2</td><td>2</td></tr><tr><td>Burst_Length</td><td>BL /* 2, 4, 8 */</td><td>8</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Mfg_Suggest_Timing</td><td>Mfg_Suggest_Timing</td><td>{0, 8, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>Extra_Timing</td><td>{1, 3, 4, 6, 6, 3, 2, 3, 3}</td></tr><tr><td>Fix_DQSS</td><td>true</td><td>true</td></tr><tr><td>Refresh_Rate_per_Bank_ms</td><td>64.0 /* 64.0 ms */</td><td>64.0</td></tr><tr><td>Refresh_Cycles_per_Bank</td><td>256 /* 256 cycles per bank */</td><td>256</td></tr><tr><td>Enable_External_Data</td><td>false</td><td>false</td></tr><tr><td>Address_Bit_Map</td><td>{{0,9},{10,24},{25,27}} /* col, row, bank (min, max) Bit Position */</td><td>{{0, 9}, {10, 24}, {25, 27}}</td></tr><tr><td>Standard_Name</td><td>&quot;none&quot; /*reads DDR_Memory_Standards.txt */</td><td>&quot;none&quot;</td></tr><tr><td>Standard_File</td><td>VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt</td><td>&quot;VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Memory_Controller</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Bank_at_a_Time</td><td>true /* false=all */</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>MC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Controller_Name</td><td>&quot;LPDDR&quot;</td><td>&quot;LPDDR&quot;</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Controller_Speed_Mhz</td><td>Bus_Speed</td><td>400.0</td></tr><tr><td>Memory_Width_Bytes</td><td>2</td><td>2</td></tr><tr><td>Bus_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Command_Buffer_Length</td><td>16</td><td>16</td></tr><tr><td>Commands_in_a_Row</td><td>16</td><td>16</td></tr><tr><td>Mfg_Suggest_Timing</td><td>Mfg_Suggest_Timing</td><td>{0, 8, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>Extra_Timing</td><td>{1, 3, 4, 6, 6, 3, 2, 3, 3}</td></tr><tr><td>Burst_Length</td><td>BL /* 2, 4, 8 */</td><td>8</td></tr><tr><td>Memory_Column</td><td>{0,12}</td><td>{0, 12}</td></tr><tr><td>Memory_Row</td><td>{13,25}</td><td>{13, 25}</td></tr><tr><td>Memory_Bank</td><td>{26,28}</td><td>{26, 28}</td></tr><tr><td>Memory_Bank_Length</td><td>round(pow(2,(Memory_Bank(1) - Memory_Bank(0) + 1)))</td><td>8L</td></tr><tr><td>DRAM_Return_Cycles</td><td>0</td><td>0</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR0&quot;</td><td>&quot;DDR0&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Input_Device_Name</td><td>&quot;Bus_2&quot;</td><td>&quot;Bus_2&quot;</td></tr></table> <h2>OUT2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Debug</td><td>&quot;Debug&quot;</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr></table> <h2>OUT</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Debug</td><td>&quot;Debug&quot;</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr></table> <h2>IN</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Debug</td><td>&quot;Debug&quot;</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr></table> <h2>Addr_Check3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Mem_Monitor&quot;</td><td>&quot;Mem_Monitor&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr></table> <h2>Addr_Check2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;D1_Monitor&quot;</td><td>&quot;D1_Monitor&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr></table> <h2>Addr_Check</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;I1_Monitor&quot;</td><td>&quot;I1_Monitor&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr></table> <h2>VM_d_Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>Device_Name + &quot;_Traffic2&quot;</td><td>&quot;MM_Traffic2&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Single_Cycle</td><td>false</td><td>false</td></tr><tr><td>Duplicate_Input</td><td>false</td><td>false</td></tr><tr><td>Start_Time</td><td>1.0E-09</td><td>1.0E-9</td></tr><tr><td>Mean_Time</td><td>1.0E-06 / Traffic_Rate_Mhz</td><td>5.0E-9</td></tr><tr><td>Data_Structure</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Name_of_Event</td><td>&quot;MM2_MyEvent&quot;</td><td>&quot;MM2_MyEvent&quot;</td></tr><tr><td>Source</td><td>&quot;MM2&quot;</td><td>&quot;MM2&quot;</td></tr><tr><td>Destination</td><td>D1_Destination_Name</td><td>&quot;SDRAM&quot;</td></tr><tr><td>Size_of_Data_Transferred</td><td>Data_Size</td><td>16</td></tr><tr><td>Address_Start</td><td>1000</td><td>1000</td></tr></table> <h2>VM_i_Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>Device_Name + &quot;_Traffic&quot;</td><td>&quot;MM_Traffic&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Single_Cycle</td><td>false</td><td>false</td></tr><tr><td>Duplicate_Input</td><td>false</td><td>false</td></tr><tr><td>Start_Time</td><td>1.0E-09</td><td>1.0E-9</td></tr><tr><td>Mean_Time</td><td>1.0E-06 / Traffic_Rate_Mhz</td><td>5.0E-9</td></tr><tr><td>Data_Structure</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Name_of_Event</td><td>Device_Name + &quot;_MyEvent&quot;</td><td>&quot;MM_MyEvent&quot;</td></tr><tr><td>Source</td><td>Device_Name</td><td>&quot;MM&quot;</td></tr><tr><td>Destination</td><td>I1_Destination_Name</td><td>&quot;NOR&quot;</td></tr><tr><td>Size_of_Data_Transferred</td><td>Data_Size</td><td>16</td></tr><tr><td>Address_Start</td><td>0</td><td>0</td></tr></table> <h2>SingleEvent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_explanation</td><td>Source-&gt;Event-&gt;SingleEvent\t</td><td>Source-&gt;Event-&gt;SingleEvent\t</td></tr><tr><td>time</td><td>0.0</td><td>0.0</td></tr><tr><td>value</td><td>true</td><td>true</td></tr></table> <h2>CA_Cache2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;D1_Cache&quot;</td><td>&quot;D1_Cache&quot;</td></tr><tr><td>Cache_Size_KB</td><td>4</td><td>4</td></tr><tr><td>Cache_Speed_Mhz</td><td>200.0</td><td>200.0</td></tr><tr><td>Cache_Bytes_per_Word</td><td>8</td><td>8</td></tr><tr><td>Bus_Width_Bytes</td><td>16</td><td>16</td></tr><tr><td>Cache_Line_Words</td><td>8</td><td>8</td></tr><tr><td>Cache_N_Associativity</td><td>4 /* 0 (Full Associaitive,1(Direct),2,4,8,16,32 */</td><td>4</td></tr><tr><td>Cache_Replacement_Policy</td><td>&quot;Least_Recently_Used&quot; /* Least_Recently_Used, Most_Recently_Used */</td><td>&quot;Least_Recently_Used&quot;</td></tr><tr><td>Cache_Write_Policy</td><td>&quot;Write_Back&quot; /* Write_Back, Write_Through */</td><td>&quot;Write_Back&quot;</td></tr><tr><td>Cache_Prefetch_Lines</td><td>1 /* 0,1,2,3... */</td><td>1</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>Next_Higher_Memory_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Snooping_Flag</td><td>false</td><td>false</td></tr><tr><td>Read_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td></tr><tr><td>Number_Statistics_Samples</td><td>1</td><td>1</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Next_Memory_Bus</td><td>true</td><td>true</td></tr></table> <h2>CA_Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;I1_Cache&quot;</td><td>&quot;I1_Cache&quot;</td></tr><tr><td>Cache_Size_KB</td><td>4</td><td>4</td></tr><tr><td>Cache_Speed_Mhz</td><td>200.0</td><td>200.0</td></tr><tr><td>Cache_Bytes_per_Word</td><td>8</td><td>8</td></tr><tr><td>Bus_Width_Bytes</td><td>16</td><td>16</td></tr><tr><td>Cache_Line_Words</td><td>8</td><td>8</td></tr><tr><td>Cache_N_Associativity</td><td>4 /* 0 (Full Associaitive,1(Direct),2,4,8,16,32 */</td><td>4</td></tr><tr><td>Cache_Replacement_Policy</td><td>&quot;Least_Recently_Used&quot; /* Least_Recently_Used, Most_Recently_Used */</td><td>&quot;Least_Recently_Used&quot;</td></tr><tr><td>Cache_Write_Policy</td><td>&quot;Write_Back&quot; /* Write_Back, Write_Through */</td><td>&quot;Write_Back&quot;</td></tr><tr><td>Cache_Prefetch_Lines</td><td>0 /* 0,1,2,3... */</td><td>0</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>Next_Higher_Memory_Name</td><td>&quot;NOR&quot;</td><td>&quot;NOR&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;NOR&quot;</td><td>&quot;NOR&quot;</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Snooping_Flag</td><td>false</td><td>false</td></tr><tr><td>Read_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td></tr><tr><td>Number_Statistics_Samples</td><td>1</td><td>1</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Next_Memory_Bus</td><td>true</td><td>true</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here\\nSource_Node Destination_Node Hop Source_Port ; \\nSDRAM MM I1_Cache output ;\\nSDRAM MM2 D1_Cache output ;\\nSwitch MM I1_Cache output ;\\nSwitch MM2 D1_Cache output ;</td><td>Enter User Documentation Here\\nSource_Node Destination_Node Hop Source_Port ; \\nSDRAM MM I1_Cache output ;\\nSDRAM MM2 D1_Cache output ;\\nSwitch MM I1_Cache output ;\\nSwitch MM2 D1_Cache output ;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\n</td><td>/* First row contains Column Names. */\\n</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table>

Demonstrates the use of the Cycle-Accurate cache and the Cycle-Accurate Memory Controller. For more details, look at the System technology IP pages for a more detailed description.

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