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ARM vs RISC-V Cores | System level Comparison-Latency, Power

August 16, 2024

Methodology for System-level Comparison of ARM vs RISC-V Cores for Latency and Power Consumption System-level analysis is the only methodology to compare the performance and power consumption of two processor architectures. Unfortunately, processor models to perform the comparison are not easily available. This article describes a performance and power comparison methodology using system-level IP between […]

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Hardware Software Partitioning- Simulations and Discussions

August 16, 2024

Hardware Software Partitioning – Simulations & Discussions Hardware/software partitioning is the concept of dividing an application’s computations into a part that executes sequential instructions on a microprocessor (the “software”) and a part that runs parallel circuits on some IC fabric like an ASIC or FPGA (the “hardware”), such as to achieve design goals set for […]

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Functional Safety for Braking System through ISO 26262

August 8, 2024

Functional Safety for Braking System through ISO 26262, Operating System Security and DO 254 Implementation of safety measures is on the rise in today’s automotive world in order to minimize the hazards in case of system malfunction. Today’s automobiles run various safety critical applications like ABS, electronic power steering, air bag sensors, radar sensing, and […]

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Reducing Power Consumption | Early System-Level Modeling

August 8, 2024

Measuring and Reducing Power Consumption Using Early System-Level Power Modeling Power evaluation in the early stages of the product design has been performed mostly using analytical methods such as spreadsheets. These spreadsheets typically contain the power for different tasks or devices and the sheet adds the worst case or the average of the power.  These […]

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Switch Design for Optimal Service Quality

July 26, 2024

Switch Design for Optimal Service Quality A large number of current-generation switches and routers operate in a multi-protocol, non-blocking, packet segmentation, packet reassembly, parallel execution environment.  The system must support quality of service (QOS) levels that take into account video frame rate constraints, switch-to-switch throttling control, packet priorities, error checking/correction, and retransmission of overflow packets […]

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Design UCIe-based Multi-die SoC with VisualSim

July 26, 2024

Architecture-stage EDA Tool VisualSim to Design UCIe-based Multi-die SoC While performance is the key factor for commercial success of any semiconductor chip, the development cost and time plays an even more critical role in the successful launch of the chip. Extremely complex and expensive semiconductor fabrication technologies such as nano-sheet FETs are used today at […]

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Optimizing Aircraft Avionics for Next-Gen Requirements

July 26, 2024

Optimizing Aircraft Avionics for Next-Gen Requirements Prior generation of avionics were built with a specific use-case in mind.  The resources were sized efficiently to match the avionics application requirements for performance, functionality, and failure.  These designs were tested using reference boards provided by the vendor.  The new generation of avionics have dynamic requirements with multiple […]

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Architecture Exploration- Managing Product Lifecycle

July 26, 2024

Architecture Exploration- Managing Product Lifecycle through Simulation Abstract To have a true closed loop design environment, a single executable must be the reference from requirements to after-sale debugging.  This encompasses several stages and each having their own challenges and requirements.  The closed loop will ensure there is accountability and tracking, thus ensuring uniform communication.  The […]

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Accelerating Architecture Exploration for FPGA Selection

July 25, 2024

Accelerating Architecture Exploration for FPGA Selection and System Design You can create an optimized specification that achieves performance, reliability, and cost goals for use in production systems. Performance analysis and early architecture exploration ensures that you will select the right FPGA platform and achieve optimal partitioning of the application onto the fabric and software. This […]

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Optimizing Consumer Electronics Architectures

July 5, 2024

Optimizing Consumer Electronics Architectures for Low-Power For a consumer application, the response time, display resolution and battery life are the top features. The lifecycle of the battery is directly proportional to its capacity, power spikes and usage profile. The battery size cannot be increased indiscriminately because of cost, space and reliability considerations. Semiconductor power loss […]

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VisualSim Architect TTEthernet

July 5, 2024

The Features of VisualSim Architect TTEthernet VisualSim TTE Library is a part of the VisualSim Networking package.  This library can be combined with models from the hardware, software, aerospace, and networking library to conduct requirements validation, system analysis, topology assessment, system architecture exploration, system validation, and testing. VisualSim Architect models are end-to-end models with the […]

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Virtual Experiments with Zynq 7000 

July 4, 2024

Virtual Experiments with Optimal System Resource Allocation in Zynq 7000 Zynq 7000 Programmable SoC from AMD-Xilinx is an FPGA device that combines processors, application programmable units, on-chip memories, memory controllers, twenty interfaces, and programmable logic. The massive processing power, number of interfaces and large logic resources make the life of system designers technically challenging. With […]

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