Processor

Exploring the implementation of a real-time video processing on a ARM SoC with hardware accelerators and power management

Power_Perf_example

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Power_Perf_examplemodel <h2>PowerTable2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Excel spreadsheet import.  The power \\ninformation is maintained here.</td><td>This is the Excel spreadsheet import.  The power \\ninformation is maintained here.</td></tr><tr><td>Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Manager_Setup</td><td>/* Power_Table.  First row contains Column Names, expressions valid for entries except Device Name.                                                 \\n                                                                                                                                                    \\n--------Device Name-------  ---------Power States------  -----Operating States------  -----------State Transitions---------  --Speed--  --Exist-- */\\n    Architecture_Block           Standby  Active  Wait     Idle  Existing  OffState  OnState  t_OnOff      Mhz       Volts   ; \\nStreaming_Board_ARM              75.0     200.0    100.0    100.0  Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_MOVE             25.0     100.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Cache            50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_HW_ACC           10.0     100.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_HW_ACC_Bus       50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_AHB_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_RAM_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_ROM_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Ext_SDRAM_Bus    50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Ext_FLASH_Bus    50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_Ext_SDRAM       150.0     350.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_Ext_FLASH       150.0     350.0    0.0      0.0    Standby   Standby   Active    1.0e-8    1000.0     1.0     ;\\nScheduler_EBU_Scheduler      \t 75.0     250.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nScheduler_LMU_Scheduler      \t 75.0     250.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nScheduler_HW_Engine\t\t200.0     600.0    0.0     10.0     Idle     Standby   Active    1.0e-7       1000.0     1.0     ;</td><td>/* Power_Table.  First row contains Column Names, expressions valid for entries except Device Name.                                                 \\n                                                                                                                                                    \\n--------Device Name-------  ---------Power States------  -----Operating States------  -----------State Transitions---------  --Speed--  --Exist-- */\\n    Architecture_Block           Standby  Active  Wait     Idle  Existing  OffState  OnState  t_OnOff      Mhz       Volts   ; \\nStreaming_Board_ARM              75.0     200.0    100.0    100.0  Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_MOVE             25.0     100.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Cache            50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_HW_ACC           10.0     100.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_HW_ACC_Bus       50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_AHB_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_RAM_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_ROM_Bus          50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Ext_SDRAM_Bus    50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ; \\nStreaming_Board_Ext_FLASH_Bus    50.0     150.0    0.0      0.0    Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_Ext_SDRAM       150.0     350.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nStreaming_Board_Ext_FLASH       150.0     350.0    0.0      0.0    Standby   Standby   Active    1.0e-8    1000.0     1.0     ;\\nScheduler_EBU_Scheduler      \t 75.0     250.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nScheduler_LMU_Scheduler      \t 75.0     250.0    0.0      0.0     Standby   Standby   Active   1.0e-8    1000.0     1.0     ;\\nScheduler_HW_Engine\t\t200.0     600.0    0.0     10.0     Idle     Standby   Active    1.0e-7       1000.0     1.0     ;</td></tr><tr><td>Async_State_Change</td><td>/* Async_State_Change.  First row contains Column Names, expressions valid for entries except Device Name.                                                 \\n                                                                                                                                                    \\n--------Device Name-------  ------------Time State--------- */\\n    Architecture_Block      State     Time_or_Express  Next ; \\n/* Scheduler_HW_Engine         Standby   1.0e-9           Idle ; */\\n</td><td>/* Async_State_Change.  First row contains Column Names, expressions valid for entries except Device Name.                                                 \\n                                                                                                                                                    \\n--------Device Name-------  ------------Time State--------- */\\n    Architecture_Block      State     Time_or_Express  Next ; \\n/* Scheduler_HW_Engine         Standby   1.0e-9           Idle ; */\\n</td></tr><tr><td>Expression_List</td><td>/* First row contains Column Names.                                                                                                                 \\n                                                                                                                                                    \\n---------Reference--------  ------------------------------------Expression----------------------------------------------------------------------- */\\n           Name                                                   Value                                                                           ; \\n</td><td>/* First row contains Column Names.                                                                                                                 \\n                                                                                                                                                    \\n---------Reference--------  ------------------------------------Expression----------------------------------------------------------------------- */\\n           Name                                                   Value                                                                           ; \\n</td></tr><tr><td>Battery_Units</td><td>Milli_Watts</td><td>Milli_Watts</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Statistics Summary&quot;</td><td>&quot;Statistics Summary&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Call_func</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>Result_A = (input.INDEX &lt; FunctionA_Call_Rate)?true:false</td><td>Result_A = (input.INDEX &lt; FunctionA_Call_Rate)?true:false</td></tr><tr><td>Output_Ports</td><td>output,output1</td><td>&quot;output,output1&quot;</td></tr><tr><td>Output_Values</td><td>input,input</td><td>&quot;input,input&quot;</td></tr><tr><td>Output_Conditions</td><td>Result_A,!Result_A</td><td>&quot;Result_A,!Result_A&quot;</td></tr></table> <h2>Scenario</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>Result_A    = (Select_Scenario == 1)?true:false\\ninput.INDEX = (Result_A == true)?(irand(1,10)):input.INDEX\\ninput.ID    = ID_Counter + 1\\nID_Counter  = ID_Counter + 1\\ninput.TIME  = TNow</td><td>Result_A    = (Select_Scenario == 1)?true:false\\ninput.INDEX = (Result_A == true)?(irand(1,10)):input.INDEX\\ninput.ID    = ID_Counter + 1\\nID_Counter  = ID_Counter + 1\\ninput.TIME  = TNow</td></tr><tr><td>Output_Ports</td><td>output,output1</td><td>&quot;output,output1&quot;</td></tr><tr><td>Output_Values</td><td>input,input</td><td>&quot;input,input&quot;</td></tr><tr><td>Output_Conditions</td><td>Result_A,!Result_A</td><td>&quot;Result_A,!Result_A&quot;</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* No Expressions. */</td><td>/* No Expressions. */</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>(powerCurrent(&quot;Manager_1&quot;, &quot;Scheduler_HW_Engine&quot;))</td><td>&quot;(powerCurrent(&quot;Manager_1&quot;, &quot;Scheduler_HW_Engine&quot;))&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A = powerManager(&quot;Manager_1&quot;)\\nPower_Usage(0) = (Result_A.Streaming_Board_ARM).Cumulative\\nPower_Usage(1) = (Result_A.Streaming_Board_Cache).Cumulative\\nPower_Usage(2) = (Result_A.Scheduler_HW_Engine).Cumulative\\nPower_Usage(3) = (Result_A.Streaming_Board_Ext_SDRAM).Cumulative\\nPower_Percent(0) = (Result_A.Streaming_Board_ARM).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(1) = (Result_A.Streaming_Board_Cache).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(2) = (Result_A.Scheduler_HW_Engine).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(3) = (Result_A.Streaming_Board_Ext_SDRAM).Cumulative / (Result_A.total).Cumulative * 100.0\\n</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A = powerManager(&quot;Manager_1&quot;)\\nPower_Usage(0) = (Result_A.Streaming_Board_ARM).Cumulative\\nPower_Usage(1) = (Result_A.Streaming_Board_Cache).Cumulative\\nPower_Usage(2) = (Result_A.Scheduler_HW_Engine).Cumulative\\nPower_Usage(3) = (Result_A.Streaming_Board_Ext_SDRAM).Cumulative\\nPower_Percent(0) = (Result_A.Streaming_Board_ARM).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(1) = (Result_A.Streaming_Board_Cache).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(2) = (Result_A.Scheduler_HW_Engine).Cumulative / (Result_A.total).Cumulative * 100.0\\nPower_Percent(3) = (Result_A.Streaming_Board_Ext_SDRAM).Cumulative / (Result_A.total).Cumulative * 100.0\\n</td></tr><tr><td>Output_Ports</td><td>output,percent</td><td>&quot;output,percent&quot;</td></tr><tr><td>Output_Values</td><td>Power_Usage, Power_Percent</td><td>&quot;Power_Usage, Power_Percent&quot;</td></tr><tr><td>Output_Conditions</td><td>true,true</td><td>&quot;true,true&quot;</td></tr></table> <h2>SingleEvent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_explanation</td><td>Source-&gt;Event-&gt;SingleEvent\t</td><td>Source-&gt;Event-&gt;SingleEvent\t</td></tr><tr><td>time</td><td>Sim_Time</td><td>0.02</td></tr><tr><td>value</td><td>true</td><td>true</td></tr></table> <h2>Power Percent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>iterationsPerUpdate</td><td>1</td><td>1</td></tr><tr><td>xInit</td><td>0.0</td><td>0.0</td></tr><tr><td>xUnit</td><td>1.0</td><td>1.0</td></tr></table> <h2>Power Usage</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>false</td><td>false</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>iterationsPerUpdate</td><td>1</td><td>1</td></tr><tr><td>xInit</td><td>0.0</td><td>0.0</td></tr><tr><td>xUnit</td><td>1.0</td><td>1.0</td></tr></table> <h2>IN</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Arch_Stats</td><td>&quot;Arch_Stats&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr></table> <h2>Timing_Diagram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Proc_Name</td><td>&quot;ARM&quot;</td><td>&quot;ARM&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus&quot;</td><td>&quot;AHB_Bus&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;RAM&quot;</td><td>&quot;RAM&quot;</td></tr><tr><td>AXI_Name</td><td>Bus_Name</td><td>&quot;AHB_Bus&quot;</td></tr><tr><td>Memory_Controller_Name</td><td>&quot;LPDDR_1&quot;</td><td>&quot;LPDDR_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>_explanation</td><td>Hardware Setup-&gt;Timing_Diagram</td><td>Hardware Setup-&gt;Timing_Diagram</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.02</td></tr></table> <h2>AMBA_AXI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Bus_Name</td><td>Bus_Name</td><td>&quot;TOP_LEVEL_AXI&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>AXI_Speed_Mhz</td><td>166.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>6.0240963855422E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2}  </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>2</td><td>2</td></tr><tr><td>Number_Slaves</td><td>2</td><td>2</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>true</td><td>true</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>2</td><td>2</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{166.0, 166.0, 166.0, 166.0, 166.0, 166.0, 166.0, 166.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Ext_SDRAM&quot;},{&quot;Ext_FLASH&quot;},{&quot;none&quot;},{&quot;none&quot;}}</td><td>{{&quot;Ext_SDRAM&quot;}, {&quot;Ext_FLASH&quot;}, {&quot;none&quot;}, {&quot;none&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{true,false,true,true,true,true,true,true}</td><td>{true, false, true, true, true, true, true, true}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,true,true}  </td><td>{false, false, true, true}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true  /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.02</td></tr></table> <h2>Mem_Select</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Memory_Selection_Top&quot;</td><td>&quot;Memory_Selection_Top&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names.              */\\nParameter_Name                 Parameter_Value  \\nPath                           none             \\nRead_File                      none             \\nSelf_Start                     false            \\nParam_Script                   none             \\nListen_to_File                 none             \\nDuplicate_Input                true             \\nProfile                        0                \\nProfile_File                   none             \\nMaximum_Loops                  1000000          \\nBlock_Reference                Block_Name       \\nPort_Order_Array               {&quot;input&quot;}      \\n</td><td>/* First row contains Column Names.              */\\nParameter_Name                 Parameter_Value  \\nPath                           none             \\nRead_File                      none             \\nSelf_Start                     false            \\nParam_Script                   none             \\nListen_to_File                 none             \\nDuplicate_Input                true             \\nProfile                        0                \\nProfile_File                   none             \\nMaximum_Loops                  1000000          \\nBlock_Reference                Block_Name       \\nPort_Order_Array               {&quot;input&quot;}      \\n</td></tr><tr><td>Ext_RAM_Hit_Rate</td><td>30</td><td>30</td></tr></table> <h2>OUT4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Arch_Stats</td><td>&quot;Arch_Stats&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr></table> <h2>VariableList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template          \\nName          Type          Value     */\\nID_Counter    local         1       ;  \\nPower_Usage   global        {0.0, 0.0, 0.0, 0.0, 0.0}  ;\\nPower_Percent global        {0.0, 0.0, 0.0, 0.0, 0.0}  ;</td><td>/* Memory Initialize Template          \\nName          Type          Value     */\\nID_Counter    local         1       ;  \\nPower_Usage   global        {0.0, 0.0, 0.0, 0.0, 0.0}  ;\\nPower_Percent global        {0.0, 0.0, 0.0, 0.0, 0.0}  ;</td></tr></table> <h2>TaskGenerator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;My_SoftGen&quot;</td><td>&quot;My_SoftGen&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Loop&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Loop&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.02</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table.txt</td><td>&quot;Instruction_Mix_Table.txt&quot;</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop               Source_Port ; \\n\\n/* forward paths. assuming that everything is cached as of now */\\nCache          RAM                ARM_Port2         output      ; \\nARM_Port2      RAM                ARM_Port4         output2     ;\\nARM_Port4      RAM                RAM_Bus_Port1     output2     ;\\n\\nCache          ROM                ARM_Port2         output      ; \\nARM_Port2      ROM                ARM_Port4         output2     ;\\nARM_Port4      ROM                ROM_Bus_Port1     output2     ;\\n\\nCache          Ext_SDRAM          ARM_Port2               output      ; \\nARM_Port2      Ext_SDRAM          ARM_Port4               output2     ;\\nARM_Port4      Ext_SDRAM          Ext_SDRAM_Bus_Port1     output2     ;\\n\\nCache          Ext_FLASH          ARM_Port2               output      ; \\nARM_Port2      Ext_FLASH          ARM_Port4         \t  output2     ;\\nARM_Port4      Ext_FLASH          Ext_FLASH_Bus_Port1     output2     ;\\n\\n/* return paths */\\nRAM             ARM                RAM_Port2         output      ;\\nRAM_Port2       ARM                RAM_Port1         output      ;\\nRAM_Port1       ARM                ARM_Port4         output      ;\\nRAM             MOVE               RAM_Port2         output      ;\\nRAM_Port2       MOVE               RAM_Port1         output      ;\\nRAM_Port1       MOVE               ARM_Port4         output      ;\\nRAM             Cache               RAM_Port2         output      ;\\nRAM_Port2       Cache               RAM_Port1         output      ;\\nRAM_Port1       Cache               ARM_Port4         output      ;\\n\\nROM             ARM                ROM_Port2         output      ;\\nROM_Port2       ARM                ROM_Port1         output      ;\\nROM_Port1       ARM                ARM_Port4         output      ;\\nROM             MOVE               ROM_Port2         output      ;\\nROM_Port2       MOVE               ROM_Port1         output      ;\\nROM_Port1       MOVE               ARM_Port4         output      ;\\nROM             Cache               ROM_Port2         output      ;\\nROM_Port2       Cache               ROM_Port1         output      ;\\nROM_Port1       Cache               ARM_Port4         output      ;\\n\\nExt_SDRAM       ARM                 Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 ARM                 Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 ARM                 ARM_Port4         output      ;\\nExt_SDRAM       MOVE                Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 MOVE                Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 MOVE                ARM_Port4         output      ;\\nExt_SDRAM       Cache               Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 Cache               Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 Cache               ARM_Port4         output      ;\\nExt_SDRAM       HW_ACC              Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 HW_ACC              Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 HW_ACC              HW_ACC_Port_1      output      ;\\n\\nExt_FLASH       ARM                Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 ARM                Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 ARM                ARM_Port4         output      ;\\nExt_FLASH       MOVE               Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 MOVE               Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 MOVE               ARM_Port4         output      ;\\nExt_FLASH       Cache               Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 Cache               Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 Cache               ARM_Port4         output      ;\\nExt_FLASH       HW_ACC              Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 HW_ACC              Ext_FLASH_Port1   output      ;\\nExt_FLASH_Port1 HW_ACC              HW_ACC_Port2      output      ;\\n\\nARM_Port4       Cache              ARM_Port2         output2     ;\\nARM_Port4       MOVE               ARM_Port1         output2     ;\\n\\nHW_ACC_Port_1    HW_ACC            HW_ACC_Port_2      output2      ;\\nHW_ACC_Port_2    HW_ACC            HW_ACC_Port_2      output2      ;\\nHW_ACC\t\tExt_SDRAM\t   HW_ACC_Port_2      output2\t;\\nHW_ACC_Port_2\tExt_SDRAM\t   HW_ACC_Port_1\toutput1     ;\\nHW_ACC_Port_1\tExt_SDRAM\t   HW_ACC_Port_1       output1     ;</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop               Source_Port ; \\n\\n/* forward paths. assuming that everything is cached as of now */\\nCache          RAM                ARM_Port2         output      ; \\nARM_Port2      RAM                ARM_Port4         output2     ;\\nARM_Port4      RAM                RAM_Bus_Port1     output2     ;\\n\\nCache          ROM                ARM_Port2         output      ; \\nARM_Port2      ROM                ARM_Port4         output2     ;\\nARM_Port4      ROM                ROM_Bus_Port1     output2     ;\\n\\nCache          Ext_SDRAM          ARM_Port2               output      ; \\nARM_Port2      Ext_SDRAM          ARM_Port4               output2     ;\\nARM_Port4      Ext_SDRAM          Ext_SDRAM_Bus_Port1     output2     ;\\n\\nCache          Ext_FLASH          ARM_Port2               output      ; \\nARM_Port2      Ext_FLASH          ARM_Port4         \t  output2     ;\\nARM_Port4      Ext_FLASH          Ext_FLASH_Bus_Port1     output2     ;\\n\\n/* return paths */\\nRAM             ARM                RAM_Port2         output      ;\\nRAM_Port2       ARM                RAM_Port1         output      ;\\nRAM_Port1       ARM                ARM_Port4         output      ;\\nRAM             MOVE               RAM_Port2         output      ;\\nRAM_Port2       MOVE               RAM_Port1         output      ;\\nRAM_Port1       MOVE               ARM_Port4         output      ;\\nRAM             Cache               RAM_Port2         output      ;\\nRAM_Port2       Cache               RAM_Port1         output      ;\\nRAM_Port1       Cache               ARM_Port4         output      ;\\n\\nROM             ARM                ROM_Port2         output      ;\\nROM_Port2       ARM                ROM_Port1         output      ;\\nROM_Port1       ARM                ARM_Port4         output      ;\\nROM             MOVE               ROM_Port2         output      ;\\nROM_Port2       MOVE               ROM_Port1         output      ;\\nROM_Port1       MOVE               ARM_Port4         output      ;\\nROM             Cache               ROM_Port2         output      ;\\nROM_Port2       Cache               ROM_Port1         output      ;\\nROM_Port1       Cache               ARM_Port4         output      ;\\n\\nExt_SDRAM       ARM                 Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 ARM                 Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 ARM                 ARM_Port4         output      ;\\nExt_SDRAM       MOVE                Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 MOVE                Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 MOVE                ARM_Port4         output      ;\\nExt_SDRAM       Cache               Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 Cache               Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 Cache               ARM_Port4         output      ;\\nExt_SDRAM       HW_ACC              Ext_SDRAM_Port2   output      ;\\nExt_SDRAM_Port2 HW_ACC              Ext_SDRAM_Port1   output      ;\\nExt_SDRAM_Port1 HW_ACC              HW_ACC_Port_1      output      ;\\n\\nExt_FLASH       ARM                Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 ARM                Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 ARM                ARM_Port4         output      ;\\nExt_FLASH       MOVE               Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 MOVE               Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 MOVE               ARM_Port4         output      ;\\nExt_FLASH       Cache               Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 Cache               Ext_FLASH_Port1   output      ;          \\nExt_FLASH_Port1 Cache               ARM_Port4         output      ;\\nExt_FLASH       HW_ACC              Ext_FLASH_Port2   output      ;\\nExt_FLASH_Port2 HW_ACC              Ext_FLASH_Port1   output      ;\\nExt_FLASH_Port1 HW_ACC              HW_ACC_Port2      output      ;\\n\\nARM_Port4       Cache              ARM_Port2         output2     ;\\nARM_Port4       MOVE               ARM_Port1         output2     ;\\n\\nHW_ACC_Port_1    HW_ACC            HW_ACC_Port_2      output2      ;\\nHW_ACC_Port_2    HW_ACC            HW_ACC_Port_2      output2      ;\\nHW_ACC\t\tExt_SDRAM\t   HW_ACC_Port_2      output2\t;\\nHW_ACC_Port_2\tExt_SDRAM\t   HW_ACC_Port_1\toutput1     ;\\nHW_ACC_Port_1\tExt_SDRAM\t   HW_ACC_Port_1       output1     ;</td></tr><tr><td>Number_of_Samples</td><td>5</td><td>5</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Cache_Utilization_Pct_Min,Cache_Utilization_Pct_Mean, Cache_Utilization_Pct_Max&quot;</td><td>&quot;Cache_Utilization_Pct_Min,Cache_Utilization_Pct_Mean, Cache_Utilization_Pct_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>TimedPlotter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Inst_Power</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>InstPowerPlot</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Instant_Power.plt</td><td>&quot;Instant_Power.plt&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>true</td><td>true</td></tr></table> <h2>Flash</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Board_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;Ext_FLASH&quot;</td><td>&quot;Ext_FLASH&quot;</td></tr><tr><td>Memory_Speed</td><td>104.0 /*MHz*/</td><td>104.0</td></tr><tr><td>Memory_Size</td><td>64 /*MB */</td><td>64</td></tr></table> <h2>SDRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Board_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;Ext_SDRAM&quot;</td><td>&quot;Ext_SDRAM&quot;</td></tr><tr><td>Memory_Speed</td><td>124.8 /*MHz*/</td><td>124.8</td></tr><tr><td>Memory_Size</td><td>64 /*MB */</td><td>64</td></tr></table> <h2>Read_Frame</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Multimedia framework\\n</td><td>Multimedia framework\\n</td></tr></table> <h2>Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>10.0e-9</td><td>1.0E-8</td></tr><tr><td>Value_1</td><td>1.0E-03</td><td>1.0E-3</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>DynamicMapper2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>Call_Fn_Low_Mapper</td><td>&quot;Call_Fn_Low_Mapper&quot;</td></tr><tr><td>Database_Lookup</td><td>None</td><td>&quot;None&quot;</td></tr><tr><td>Database_Expression</td><td>None /* Advanced Feature: can use for any DB_Fld_Name below with database name */</td><td>&quot;None /* Advanced Feature: can use for any DB_Fld_Name below with database name */&quot;</td></tr><tr><td>Task_Name</td><td>A_Task_Name</td><td>&quot;A_Task_Name&quot;</td></tr><tr><td>Task_Destination</td><td>Board_Name + &quot;.ARM&quot;</td><td>&quot;Board_Name + &quot;.ARM&quot;&quot;</td></tr><tr><td>Task_Instruction</td><td>A_Instruction</td><td>&quot;A_Instruction&quot;</td></tr><tr><td>Task_ID</td><td>10</td><td>&quot;10&quot;</td></tr><tr><td>Task_Priority</td><td>A_Priority</td><td>&quot;A_Priority&quot;</td></tr><tr><td>Task_Time</td><td>A_Time</td><td>&quot;A_Time&quot;</td></tr><tr><td>Task_Plot_ID</td><td>10</td><td>&quot;10&quot;</td></tr></table> <h2>DynamicMapper</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>Call_Fn_High_Mapper</td><td>&quot;Call_Fn_High_Mapper&quot;</td></tr><tr><td>Database_Lookup</td><td>None</td><td>&quot;None&quot;</td></tr><tr><td>Database_Expression</td><td>None /* Advanced Feature: can use for any DB_Fld_Name below with database name */</td><td>&quot;None /* Advanced Feature: can use for any DB_Fld_Name below with database name */&quot;</td></tr><tr><td>Task_Name</td><td>A_Task_Name</td><td>&quot;A_Task_Name&quot;</td></tr><tr><td>Task_Destination</td><td>Board_Name + &quot;.ARM&quot;</td><td>&quot;Board_Name + &quot;.ARM&quot;&quot;</td></tr><tr><td>Task_Instruction</td><td>A_Instruction</td><td>&quot;A_Instruction&quot;</td></tr><tr><td>Task_ID</td><td>9</td><td>&quot;9&quot;</td></tr><tr><td>Task_Priority</td><td>A_Priority</td><td>&quot;A_Priority&quot;</td></tr><tr><td>Task_Time</td><td>A_Time</td><td>&quot;A_Time&quot;</td></tr><tr><td>Task_Plot_ID</td><td>9</td><td>&quot;9&quot;</td></tr></table> <h2>ANALYSIS_PLOT_SW</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Video_Frames.plt</td><td>&quot;Video_Frames.plt&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>true</td><td>true</td></tr></table> <h2>HW_ACC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Acc_Name</td><td>&quot;HW_ACC&quot;</td><td>&quot;HW_ACC&quot;</td></tr><tr><td>Board_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Acc_Speed</td><td>100.0 /*MHz*/</td><td>100.0</td></tr><tr><td>Time_between_Tasks_NS</td><td>300.0</td><td>300.0</td></tr><tr><td>Frame_Size_In_Words</td><td>10</td><td>10</td></tr><tr><td>Acc_Bus_Speed</td><td>50.0 /*MHz*/</td><td>50.0</td></tr><tr><td>ToSleep</td><td>1000.0</td><td>1000.0</td></tr></table> <h2>Rotate_Frame</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>YUV_420 =&gt; YUV_444 format conversion\\nmap from excel sheet\\nwrite to Ram. \\nuse Excel sheets</td><td>YUV_420 =&gt; YUV_444 format conversion\\nmap from excel sheet\\nwrite to Ram. \\nuse Excel sheets</td></tr><tr><td>process_next_block_trigger</td><td>1</td><td>1</td></tr><tr><td>Frame_Size</td><td>10</td><td>10</td></tr><tr><td>SW_to_HW_Map_Name</td><td>Select_Partitioning</td><td>&quot;SW&quot;</td></tr></table> <h2>Sensor</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Camera</td><td>Camera</td></tr><tr><td>Traffic_Rate_Mbps</td><td>3.0 /* M Bits per Second */</td><td>3.0</td></tr><tr><td>X</td><td>176 /* Pixels */</td><td>176</td></tr><tr><td>Y</td><td>144 /* Pixels */</td><td>144</td></tr><tr><td>D</td><td>8 /* Depth Bits */</td><td>8</td></tr><tr><td>XYBytes</td><td>(X * Y * D) / 8</td><td>25344</td></tr><tr><td>Frame_Priority</td><td>0</td><td>0</td></tr><tr><td>Frame_ID_Offset</td><td>1000</td><td>1000</td></tr><tr><td>Time_per_Image</td><td>cast(double, (X * Y * D)) / (Traffic_Rate_Mbps * 1.0E06)</td><td>0.067584</td></tr><tr><td>read_frame_trigger</td><td>2</td><td>2</td></tr></table> <h2>Video_post_proc</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Deblocking \\nDeRinging\\nMapped from excel sheet</td><td>Deblocking \\nDeRinging\\nMapped from excel sheet</td></tr></table> <h2>display</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>DMA transfers frames from \\nmemory to DIF in bursts\\nGenerate DMA requests</td><td>DMA transfers frames from \\nmemory to DIF in bursts\\nGenerate DMA requests</td></tr><tr><td>sendToLCD</td><td>2</td><td>2</td></tr></table> <h2>Format_conv</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>YUV_420 =&gt; YUV_444 format conversion\\nmap from excel sheet\\nwrite to Ram. \\nuse Excel sheets</td><td>YUV_420 =&gt; YUV_444 format conversion\\nmap from excel sheet\\nwrite to Ram. \\nuse Excel sheets</td></tr></table> <h2>Render_Frame</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>windowing, downscale, mirroring\\nupscale\\n\\nmap from excel sheet</td><td>windowing, downscale, mirroring\\nupscale\\n\\nmap from excel sheet</td></tr></table> <h2>Decode_Frame</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>MPEG decoder. \\n</td><td>MPEG decoder. \\n</td></tr></table> <h2>Delay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Delay_Value</td><td>0.00001</td><td>&quot;0.00001&quot;</td></tr></table> <h2>Utilization</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>min,mean,max</td><td>min,mean,max</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>false</td><td>false</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>ARM_SUBSYSTEM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Board_Name</td><td>Board_Name</td><td>&quot;Streaming_Board&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;ARM&quot;</td><td>&quot;ARM&quot;</td></tr><tr><td>Processor_Speed</td><td>200</td><td>200</td></tr><tr><td>Co_Processor_Name</td><td>&quot;MPEG&quot;</td><td>&quot;MPEG&quot;</td></tr><tr><td>Cache_Speed</td><td>166 /*MHz*/</td><td>166</td></tr><tr><td>Cache_Size</td><td>256 /*KB*/</td><td>256</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>Next_Memory</td><td>&quot;RAM&quot;</td><td>&quot;RAM&quot;</td></tr><tr><td>CoProcessor_Speed</td><td>Processor_Speed * 2</td><td>400</td></tr><tr><td>I_Cache_Size</td><td>&quot;16&quot; /*KB*/</td><td>&quot;16&quot;</td></tr><tr><td>D_Cache_Size</td><td>&quot;8&quot; /*KB*/</td><td>&quot;8&quot;</td></tr><tr><td>RAM_Size</td><td>8 /*KB*/</td><td>8</td></tr><tr><td>ROM_Size</td><td>96 /*KB*/</td><td>96</td></tr><tr><td>Bus_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>AXI_Speed_Mhz</td><td>166.0</td><td>166.0</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_ARM&quot;</td><td>&quot;AXI_ARM&quot;</td></tr><tr><td>Transaction_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Cache_Name2</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr></table> <h2>MOVE_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Instruction set of the MOVE coprocessor according to MOVE TRM. </td><td>Instruction set of the MOVE coprocessor according to MOVE TRM. </td></tr><tr><td>Instruction_Set_Name</td><td>&quot;MOVE_INSTR&quot;</td><td>&quot;MOVE_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n   Mnew  Rx  Ry  Rz       ;\\n   VPU INT_1          ;\\n \\nbegin INT_1           \t  ; \\n   UMRC 1                 ; /* mapped to MRC */\\n   UMCR 1                 ; /* mapped to MCR */\\n   UMBBR 1                ; /* mapped to MRC */\\n   UMRBB 1                ; /* mapped to MCR */\\n   UBBLD 1                ; /* mapped to LDC */\\n   USALD 2 3              ; /* mapped to LDC. depends on CR_BYO */\\nend   INT_1               ;</td><td>/* Instruction Set or File Path. */\\n   Mnew  Rx  Ry  Rz       ;\\n   VPU INT_1          ;\\n \\nbegin INT_1           \t  ; \\n   UMRC 1                 ; /* mapped to MRC */\\n   UMCR 1                 ; /* mapped to MCR */\\n   UMBBR 1                ; /* mapped to MRC */\\n   UMRBB 1                ; /* mapped to MCR */\\n   UBBLD 1                ; /* mapped to LDC */\\n   USALD 2 3              ; /* mapped to LDC. depends on CR_BYO */\\nend   INT_1               ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC VPU            ; /* two execution units */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n   VPU  INT_2                ; /* MOVE execution unit */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 4               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   LD_LDR 1 5                ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;\\n\\nbegin INT_2                  ;\\n   UMRC 1                    ; /* mapped to MRC */\\n   UMCR 1                    ; /* mapped to MCR */\\n   UMBBR 1                   ; /* mapped to MRC */\\n   UMRBB 1                   ; /* mapped to MCR */\\n   UBBLD 1                   ; /* mapped to LDC */\\n   USALD 2 3                 ; /* mapped to LDC. depends on CR_BYO */\\nend   INT_2                  ;\\n</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC VPU            ; /* two execution units */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n   VPU  INT_2                ; /* MOVE execution unit */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 4               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   LD_LDR 1 5                ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;\\n\\nbegin INT_2                  ;\\n   UMRC 1                    ; /* mapped to MRC */\\n   UMCR 1                    ; /* mapped to MCR */\\n   UMBBR 1                   ; /* mapped to MRC */\\n   UMRBB 1                   ; /* mapped to MCR */\\n   UBBLD 1                   ; /* mapped to LDC */\\n   USALD 2 3                 ; /* mapped to LDC. depends on CR_BYO */\\nend   INT_2                  ;\\n</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table>
Mouse over the icons to see their parameters. Click on composites and plotters to reveal their contents (if provided).

Introduction

VisualSim is a modeling and simulation software used for the architecture exploration of electronics systems, and semiconductors.  Using this environment, designers can construct graphical virtual models of their proposed system and conduct performance, power and functional analysis.

This is an example of the performance modeling using a set of standard IP blocks and a custom behavior flow diagram. Purpose of this model is to select the hardware platform for the target MPEG video application. The requirement is processing 13,000 matrices in 20 ms at less than 1 watt of power.

The model has behavior definition, hardware architecture, and the mapping. Hardware platform has ARM 926S, DSP, AHB, AXI, SRAM, Flash, SDARM and Hardware accelerator. Block diagram of the proposed system is as shown in figure below

The following has been considered while modeling :-
1. HW architecture constitutes processor, cache, memory, bus and peripheral modules.
2. SW architecture constituting dummy drivers mapped to C code & a real use case with SW blocks as models
3. HW -SW partitioning with appropriate results which show the various tradeoffs done.

Simulation Model

User can change parameters and conduct varieties of analysis to meet performance and power requirements.
We have defined the behavior definition as a flow diagram and is represented as green blocks at the bottom. Each green blocks represents a specific task of the application. Flow diagram approach of defining the software behavior flow is the most reliable and advantageous in terms of representation and mapping. These tasks are mapped on to the target architetcure defined above, during architecture exploration one can easily modify the combination of mapping tasks on to the hardware architetcure elements to achieve optimal performance and power requirements.

Configuration:

Select the following for different simulation runs :-
1.  Select_Scenario : This selects whether you want to run the basic application or do HW/SW partitioning
2. Partitioning : Choose SW or HW for the Rotation Algorithm and see results

3. Simulation time : Run simulation for a longer time to see various plots

4. Every architecure block is configurable via several parameters like frequency, size etc.

In this model we have considered 2 different approaches to meet the requirements, one is to process all applications in software, and the other is to move a few processing-intensive applications to hardware accelerators to improve the performance.

We are focusing on two metrics- the number of video frames, and the total power consumed.

We are expecting about 13K matrices of video frame keeping power consumption under 1 w. Initially run simulations with default settings, make sure that the paarmeter Partitioning is set to SW. The results and plots show that when the tasks are processed in software, we get 6600 matrices in 20 ms and the power consumption is under 1 watt. The power is fine but we do not meet the performance criteria. As we were not meeting the performance requirements while running all tasks on ARM, we found that moving some critical tasks such as rotate frame task on to a accelerator would help us in achieving performance.When we move the rotate frame application to the hardware accelerator by modifying the parameter value "Partitioning" to "HW", the performance improves substantially to 14,000 matrices but power consumption is at 1.6 W. We now introduce power gating for the hardware accelerator by turning it off when not used. To do this set the parameter "Enable_Pwr_Gating" to true. The performance drops to 13,000 matrices but the power consumption is under 1 watt.  So, we can see the trade-off.

Results

If the model runs correctly, the result should look like:

Partitioning with SW IP:

Partitioning with HW IP



Partitioning with HW IP with Power gating algorithm


References

[1] VisualSim documentation, Mirabilis Design