Abstract The RISC-V architecture offers unparalleled flexibility in processor design, allowing custom instruction sets, memory hierarchies, and peripheral configurations. This study presents a model-driven approach using VisualSim Architect to explore the performance, power, and functional trade-offs of RISC-V cores in complex system-on-chip (SoC) environments. We simulate multiple RISC-V microarchitectures with configurable pipeline stages, cache hierarchies, […]
Read more