Channel

discrete communication channel model

Quick Explanation

  • Supports modeling of virtual channels, DMA, wireless, buses and multiple execution step software tasks
  • Supports identification of errors and lost packets and force retransmissions
  • Supports multiple channels that works in parallel
  • Supports various parameters for specifying channel width, packet size, channel rate, and number of channels
  • Supports re-ordering data in the queue according to the packet priority

Protocol

  • Wireless and wired channels
  • Communication link between FPGA
  • Links between embedded systems or boards

Channel

The Channel blocks emulate multiple parallel flows like a network, wireless or sewage flow.  The block contains a single queue that feeds into multiple channels or a queue plus channel configuration. The queue is reordered based on priority.   The Channel blocks can be used to model a communication channel, serial link, DMA channel to memory, software task sequence based on channel and task type, and virtual channels.

The Channel blocks provide the infrastructure to extend the ability of the Queue and Server.  The Queue holds the transaction and sends it on the channel when the channel becomes free. The transaction can go through a sequence or delays, resource consumption, logic and a decision on success or retry.  The retry can force the packet to go back into the queue and resent.  Here the implementation details can be logic plus delay.  Example use of the reject are noise (communication channel) and buffer overflow (memory).

Stop_n_wait - implements delay based on the uniform random length of the packets