Clock Tree

A clock tree is a clock distribution network within a system or hardware design. In VisualSim clock tree is implemented in multiple ways. There is the clock tree for hardware implementation.  There are clocks that can trigger functionality within hierarchical blocks.  Then there are DQ Flipflops to align transaction to clock boundaries. There are network clocks that are triggered across the network to align all devices on a network in a distributed system.

It includes the clocking circuitry and devices from clock source to destination. The complexity of the clock tree and the number of clocking components used depends on the hardware design. Since systems can have several ICs with different clock performance requirements and frequencies, a “clock tree” refers to the various clocks feeding those ICs. It’s often the case that a single reference clock will be cascaded and synthesized into many different output clocks, resulting in a diagram that looks a bit like a sideways tree trunk. The “trunk” is the reference clock and the “branches” are the various output clocks.

Clock trees can be both very complex with many timing components and very simple with a single reference and a few copies. Of course, their complexity depends on the system they support.