Board and System Interfaces

PCI/PCIx
Bus to connect hardware discrete components on a board. Used to evaluate the latency impact
Enhanced PCI BAE Systems
PCIe
High speed serial bus for fast access to memory and storage. Also works with NVMe
RapidIO
High-performance packet-switched, interconnect technology. Supports Chip-Chip, Board-Board (Backplane), Chassis-Chassis integration
IDT Vendor Product
IDT implementation for wireless base station infrastructure, high performance computing, data centers, server, video, imaging, military and embedded computing
FibreChannel
High-speed network technology (from 1 to 128 Gbps) providing in-order, lossless delivery of raw block data, from computer data storage to servers
NVMe
High-speed network technology (from 1 to 128 Gbps) providing in-order, lossless delivery of raw block data, from computer data storage to servers.
Firewire
Serial bus architecture for high-speed data transfer
VME
High speed and high performance bus system with powerful interrupt management and multiprocessor capability
VPX
Switched fabric for cost-effective 10Gb Ethernet and PCI-Express networked systems
Spacewire
SpaceWire utilizes asynchronous communication and allows speeds between 2 Mbit/s and 400 Mbit/s
OpenVPX
OpenVPX replaces VME and VXS standards in defense designs

Overview

The RapidIO architecture is a high-performance packet interconnect technology whichsupports messaging, read/write and cache coherency semantics. VisualSim RapidIO is a very flexible modeling environment for the optimization of the RIO networks in advance of hardware availability. The tool enables users to gauge power and performance in advance of systems development, and to identify the overall gains of using RapidIO over existing interconnect technologies. The RIO library blocks are provided as unencrypted, unrestricted access to the source code and can accommodate proprietary changes.

Standards Supported

The RapidIO Specification Revision 1.1
The RapidIO Specification Revision 1.2
The RapidIO Specification Revision 2.0
The RapidIO Specification Revision 2.1

Features

RapidIO library consists of an end-point and a switch module, the combination of which can be used be used to construct the RIO topology.
Define vendor or custom components by configuring an array of parameters per entity or for the whole system.
Create randomized and distributed-based traffic patterns with variable sizes, types, priority and mailbox allocation

Device parameters include RIO Speed, Interface speed, Simulation time, Bit Error Rate, Overhead bytes, and Custom Algorithm file.
Model internal packet processing with random delays for generation of requests and responses.

Working and Usage

Complete systems using RIO network can be constructed with other VisualSim libraries such as processors from TI and Freescale, memories, storage devices, buses such as PCI, PCIe, networking devices such as Ethernet and Fiber Channel, statistical traffic generators and FPGA boards.
The unique VisualSim fault generator and the power manager can be incorporated into the RIO model for accurate system operation, logical flow tracing, deadline monitoring and predicting use case effects.
A high-performance RIO Node works in conjunction with a Serial Switch to create a RapidIO bus where the node provides the logic for master slave message processing, while the switch provides the channels and timing required by the RapidIO protocol.

Reports and Analysis

Statistics for latency, and mailbox and link throughputs.
Buffer usage at end-points

System energy and average power for end-points and links
Generate flow trace at packet level and review activities packet-by-packet, flow-by-flow, endpoint-by-endpoint, and link-by-link.

IDT Vendor Product