Interfaces

Integration to a variety of third-party tools- Python, MatLab, Excel, Trace files, SystemC and Verilog

Quick Explanation

  • Predefined library blocks
  • All interface files provided
  • Templkate-based wrapper generation

Protocol

  • MatLab
  • SystemC 2.3.1
  • Verilog
  • Excel 2016
  • Trace files from JTAG, VCD and CSV
  • Python

MatLab

The VisualSim Matlab interfaces with the Matlab engine, evaluate Matlab expressions and return the results to VisualSim. The Matlab interface has been fully tested under Windows, OSX and Linux. The MatLab install must be mounted on the local machine for this interface to work correctly. There are a sequence of settings that must be completed before the interface can be first invoked.

Python:

An actor of this class executes a Python script. There are two versions of this actor provided in the ModelBuilder libraries. The one called “PythonActor” has an input port and an output port; to view or edit its Python script, look inside the actor. The second version is called “PythonScript” and has no ports; to view or edit its Python script, select Configure (or double click on the icon).

STK Toolkit:

This block initializes the communication with Satellite Toolkit and is the conduit for transmitting and receiving data to STK. It completes a connection from ‘STK_Port’ blocks that match the STK_Interface_Name parameter. This block allows single or multiple points of distribution.

SystemC

SystemC is an event-driven simulator providing hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. SystemC use spans design and verification from concept to implementation in hardware and software. SystemC provides an interoperable modeling platform which enables the development and exchange of very fast system-level C++ models. It also provides a stable platform for development of system-level tools. The library provides a set of data types implementing various data representations needed for hardware modeling and certain types of software programming. These include 2-valued and 4-valued bit vectors of arbitrary width, and fixed-point representations. Also included in the core language are modules and ports for representing structure, as well as interfaces and channels that describe communication. Finally, the library includes a set of built-in primitive channels that have wide use such as signals and FIFOs. A SystemC system consists of a set of one or more modules. Modules provide the ability to describe structure. Modules may contain processes, ports, internal data, channels, and instances of other modules. All processes are conceptually concurrent and can be used to model the functionality of the module. Ports are objects through which the module communicates with other modules. The internal data and channels provide for communication between processes and maintaining module state. Module instances provide for hierarchical structures. The interface, port, and channel structure provides for great flexibility in modeling communication and in model refinement.

The SC_Cosim block is used to instantiated an existing SystemC file to the simulation. One instance of the SC_Sim is required for a timed simulation. If the interface is purely functional and timing is not required, SC_Sim will not be instantiated. SC_Cosim is used to add each instance of a SC_Module. To view a SystemC model in the BDE, click here. If you are using the TLM 2.0 type modeling, use the TLM_Cosim block.

Verilog

The Verilog_Cosim block is instantiated in a model at the location where an existing Verilog file must be added to the simulation. If a Verilog_Sim is also instantiated in the model, then the interface of this model with Verilog transfers time across the interface. If the interface is purely functional and no timing needs to be transfered, then the simulation can be an event-triggered. The Verilog_Sim will not be instantiated in this case.

The Use Model for the Verilog_Cosim Block is to add Verilog_Cosim blocks within a model where ever a connection to Verilog is desired. One ‘Verilog_Sim’ block per Verilog model is needed in the case of the ‘Timed Interface’.

To use the Verilog interface, a GNU gcc compiler is required and the Verilog Simulator. If you using the 32-bit interface, then use the 32-bit gcc. Similarly, the 64-bit version must use a 64-bit gcc compiler. The Windows Installer, Linux Installer and MAC Installer are available at the respective links. The default support is for ModelSim.