PCIe

Four Root Complex are connected to multiple DRAM across a PCIe bus

PCIe_AXI_model27

Browsable image of the model.

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PCIe_AXI_model27model <h2>ExpressionList4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>TNow - input.TIME</td><td>&quot;TNow - input.TIME&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Source = &quot;Source1&quot;\\ninput.A_Destination = &quot;DRAM&quot;\\ninput.A_Command = &quot;Read&quot;\\ninput.A_Bytes = 1024\\ninput.A_Priority = 1\\ninput.A_Task_Flag = true</td><td>input.A_Source = &quot;Source1&quot;\\ninput.A_Destination = &quot;DRAM&quot;\\ninput.A_Command = &quot;Read&quot;\\ninput.A_Bytes = 1024\\ninput.A_Priority = 1\\ninput.A_Task_Flag = true</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>Latency2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>DeviceInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO&quot;</td><td>&quot;IO&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;A_Destination&quot;</td><td>&quot;A_Destination&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Traffic2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>1.0</td><td>1.0</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>TNow - input.TIME</td><td>&quot;TNow - input.TIME&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Source = &quot;Source1&quot;\\ninput.A_Destination = &quot;DRAM&quot;\\ninput.A_Command = &quot;Read&quot;\\ninput.A_Bytes = 1024\\ninput.A_Priority = 1\\ninput.A_Task_Flag = true</td><td>input.A_Source = &quot;Source1&quot;\\ninput.A_Destination = &quot;DRAM&quot;\\ninput.A_Command = &quot;Read&quot;\\ninput.A_Bytes = 1024\\ninput.A_Priority = 1\\ninput.A_Task_Flag = true</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>AXI_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_Top&quot;</td><td>&quot;AXI_Top&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2}  </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>16</td><td>16</td></tr><tr><td>Number_Slaves</td><td>8</td><td>8</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DRAM&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;DRAM&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false}  </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true  /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr></table> <h2>Bridge</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge&quot;</td><td>&quot;Bridge&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>PCIe_Bus2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_2&quot;</td><td>&quot;PCIe_2&quot;</td></tr><tr><td>Number_of_Lanes</td><td>16 /* Can be an array */</td><td>16</td></tr><tr><td>Slave_Buffer</td><td>512  /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512  /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>1.0E-3</td><td>1.0E-3</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16  /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12}  /* Master, Endpoint  Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64  /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128  /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0  /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0  /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6  /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2  /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_2  /* Per Lane */</td><td>500.0</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5  /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;DRAM&quot;},{&quot;DRAM_2&quot;},{&quot;DRAM_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;}}</td><td>{{&quot;DRAM&quot;}, {&quot;DRAM_2&quot;}, {&quot;DRAM_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr><tr><td>Device_Attached_to_Slave_port</td><td>{}</td><td>{}</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>DeviceInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO2&quot;</td><td>&quot;IO2&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;A_Destination&quot;</td><td>&quot;A_Destination&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 5.0, Prefetch 6.0, Write 7.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 5.0, Prefetch 6.0, Write 7.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>SDR</td><td>SDR</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table> <h2>Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>1.0</td><td>1.0</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table>