Integrated_DSP_ARM_Platform_wout_DMA

ARM7 and Ti C6X DSP Semiconductor Platform

This model demosntrates the use of VisualSim for constructing models of common semiconductor platforms that are used in multimedia, communication and DSP applications. This VisualSim model contains traffic generators, software sequence generators, peripherals, processors, DSP, DMA, memory controller, memories, caches, bridges and buses to cover the entire system definition. This model contains a combination of defined protocols such as AHB and DDR, and custom modules such as the Multi-Port Multi-channel (MPMC) memory controller. All the defined blocks in the model using standard components from VisualSim modeling library, primarily the Hardware_Modeling library. The model also shows how blocks can be configured to perform the specific intent in your design.

The model consists of two ARM7 connected to shared Cache and DDR DRAM. The request arrives at the Ethernet and PCI interfaces from external devices or the network. The larger size packets are first transfered to memory using a DMA operation. When the transfer has been completed, an interrupt is sent to the processor. The sequence of software execution starts at the respective ARM processor. Each ARM processor has a specific sequence of code that it executes. The executable code is modeled as a series of binary instructions that are sent to the processor module. The software can be distributed in different sequences across the two processors.

The processor accesses the cache and DDR memory for both instructions and data access. Wen the processor completes the instructions, the processor sends an interrupt via a local bus to the DSP. The DSP does a sequence of processing and connects to the memory using a proprietary memory controller.

The model demonstrates the construction of both multi-core and MIMD processor architectures using the VisualSim Processor block.

The output reports looks at four parts- timing diagram, power, latency and statistics.

• The power plots show the average and peak consumption over the period of the software processing. There is an additional power plot that shows the depletion of battery. This plot is useful if the application is driven by a battery. An extension to this study can determine the requirement of the charging source and the number of functions that can be supported by the current battery capacity.
• The utilization plot shows the usage of the three processors. This will determine the better distributon of the software tasks.
• The statistics text display shows the activity by percentage and by data size. This gives a gauge for sizing the different devices in the system. For example the utilization difference between the processor and the pipeline is quote dramatic indiciating the pipeline is better utilized than the overlap processor devices.
• The latency plot shows the delay for the two processor. Notice that the tasks on ARM_1 takes longer to complete relative to ARM_2. Also, for the same software task to complete, the time distribution is quite large. This indicates the delays assoicated with the memory and DMA accesses.
• The timing diagram show the relative activity between all the devices. This helps identify any dependency that are causing the increased latency.