NoC

Designing the Noc topology for processor, DMA and accelerator devices

Semiconductor Buses

AMBA
Coming Soon
I2C Daisy
Multiple slave sources send packets to a Master sub-system using a I2C daisy chain
I2C Star
Multiple slave sources send packets to a Master sub-system using a I2C star chain
NoC
Designing the Noc topology for processor, DMA and accelerator devices
AMD Infinity Switch
Designing a SoC or embedded system using the open-standard NoC. Slight variation as there are some additional channels and an optional Forwarding Table at the Router.

NoC_Model_V14

Browsable image of the model.

To download OpenWebStart click on the links -
Windows- Compatibility:Windows 10 or higher (*)
macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
For an executable version,
Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.

http://support.microsoft.com/gp/howtoscript

A Network on Chip (NoC) is typically a communication subsystem on an IC. They are commonly used in conjunction with the cores within SoCs to bring out notable improvements to the entire system over conventional bus interconnections.