Hardware Devices

Communication Channel
Define a serial channel, parallel channel, FPGA-to-FPGA link, Aurora communication channel, and wireless channel with BER.
PCIe-to-AHB Bridge
Bridge connects the Processor on an AHB bus to the DRAM on a PCIe Bus
AHB-to-AXI Bridge
Shows a network containing a AHB connected to an AXI bus via bridge
DMA
DMA is connected to Slave devices and I/O across the PCIe bus
Switch/Crossbar/Serial Switch
Model shows the use of the Switch in managing connections between a large number of Masters and Slaves
UART
Demonstrates the use of the UART and USART blocks in VisualSim

Stop_n_Wait_w_Channel

Browsable image of the model.

For an executable version,
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To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.

http://support.microsoft.com/gp/howtoscript

Channels represent connectivity between two or more inputs and output interfaces.

Channel Modeling

This models demonstrates the use of the Channel SmartBlock in VisualSim to define a complex channel architecture. In this system, a channel is created between a transmitter and a receiver. The transmitter sends a single packet and waits for an acknowledge before sending another packet. If it receives a negative acknowledge across the same channel, then the packet is retransmitted. The channel can be defined using parameters such queue length, delay through the channel, number of channel streams and average packet size.

This Model generates Stop_n_Wait DSs and delays based on the uniform random length of the packets. If the noise is less than (2) in a range from 0 to 100, then a negative acknowledge is generated and retransmitted through the channel. The negative acknowledge is retransmitted through Channel_Complete.

Communication Channel

Hardware Devices

Stop_n_Wait_w_Channel

Channel Modeling