Basic_Processor_Model
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"A model of the Nehalem processor is presented with the goal of analyzing the performance of legacy software applications in a multi-core environment. Multi-core architectures continue to expand, with 4 and 8 core systems readily available to the market, and with 16 and 24 core systems already starting to appear. A major concern is to know how software applications will scale and/or adjust to the increasing availability of multi-core processing systems. Previous research indicates that as the number of cores increases, a legacy application will actually realize a decrease in performance due to resource contention at L3 cache levels as well as main memory. Therefore, a model of the Nehalem processor was developed using the VisualSim tool in order to capture current performance and then predict behavior as the number of cores increases. This will allow software developers to be ready for new multi-core processing systems before they actually are available to the market. It will also allow for the definition of new software development paradigms applied to multi-core systems.
To address this problem, a model of the Nehalem processor [1] system was developed using a tool called VisualSim Architect from Mirabilis Design Inc [3]. The Nehalem is the codename for Intel’s micro-architecture for multi-core processing systems. The main focus of the model was to describe processing behavior at all levels of cache and main memory systems. The input to the model would be empirical instruction and data operations of a software application from which the model would describe the performance. This would allow for the identification of bottlenecks. Parameters such as cache size, replacement policies, and bus width could then be adjusted to determine if performance can be improved. It would also indicate where an application was experiencing a bottleneck. The software could then be reviewed to determine if performance improvements could be realized. Because the model could be modified to implement more processing cores, this would allow for performance analysis and improvement before a specific multi-core system had been released to the market."