Using VisualSim Library Blocks


Application Templates Based on Libraries: The Pre-Built models provide a convenient mechanism to learn quickly all the features of VisualSim. Every operation of each block is explained using examples. There are examples that can be used as a starting point for many design exploration studies. All examples are documented.
VisualSim Modeling Libraries
Table of Content

Basic Graphical Operation	Model Setup	Traffic	Results
How-to-Tasks Repeat Dynamic Instantiation Applet Parameter Altering the BDE View Unit Static Unit Non-Static Unit Type Sketched Source RegEx Expression Language Eg.	Draw Tools Parameter Simulator Variables Hierarchical_Blocks FSM Utility	Clock Event Interactive Traffic Delay	PlotManager 3D Interactive Creator Plotter Statistics_Generator Text

File IO	Behavior	Mapper	Resources
File Import Database	ExpressionList Script Fork Join IN OUT Execution Control Switching Processing Mux	Mapping	Smart_Resource/Queues Channel and Pipeline Event Queue Quantity-based Timed-Queue Scheduler/System Resource

Power Modeling	Hardware Setup	Processor Generator	Memory
Power_Manager Battery	Architecture_Setup Utility	Core_Architecture Vendor_Specific Processor Cache	Memory

Hardware Devices	Interfaces and Buses	FPGA's	System Language
Bus_Switch_Ctrl	Standard_Bus Emerging_Bus_Standard	Xilinx_FPGA	C_and_CPP MatLab Python Satellite Toolkit

Hardware Language	Data Access	Math Operations	Application
SystemC Verilog	Database Corba SQL Database File_Access Socket Serial io Excel XML Parsing	Array Boolean Counter Distributions Logic Math and Trig Parser Transform String Operations	Auto Aerospace Networking Wireless_Sensor

Algorithms
Analog Control_Systems Image_Processing Petri_net Signal_Processing

Demonstration Models and Example Systems
Basic Graphical Operations

How-to-Tasks Demonstrates the basic usage of the hierarchical blocks, ports and block-to-block connection Repeat This feature provides the facility to pause and save simulation data to continue simulation even after closing the tool Demo Model is available in VS_AR\doc\Training_Material\How_to_tasks\Repeat directory Dynamic Instantiation Using the Dynamic Instantiation to make the multiple instantiation of a single without cluttering the model diagram Applet Basic understanding of including Applets in the documentation Parameter Shows the use of the int-range/ slider parameter Altering the BDE View Shows the use of special XML parsing functions for altering the screen view Unit Explains the rationale and the usage of the Unit System in VisualSim Static Unit Provides the means to constrain a model in terms of the allowable units of measure Non-Applet Static Unit Description Provides the means to constrain a model in terms of the allowable units of measure Type This explains the polymorphic nature of the Type System and how the block port adapts their data type based on the port that it is connected too. Sketched Source Use the graph to create new interactive sources

RegEx Function

Built-in RegEx Function Array Functions Demo Model Description Automatic Casting Demo Model Description Basic Mathematical Functions Description Cast Demo Model Description Constant Demo Model Description Data Structure and Tokens Demo Model Description Database Demo Model Description Distributions Demo Model Description Event Description Find and Search Description Functions for Evaluating Expression Description General Description Hardware Architecture Routing Demo Model Description I/O Functions and Other Miscellaneous Functions Description IO Methods Description Linear Bus Extension Description Matrix, Array and Data Structure Functions Description Memory Description Power Modeling Demo Model Description Queue and Scheduler Methods Demo Model Description Signal Processing Functions Description Standard Operators Description Statistics Description String Constants Description SystemC Description Time Description Trigonometric Functions Description Virtual Commands Description

Model Setup

Draw Tools Using Annotation Parameter Using Parameter Using ParameterSet Using SharedParameter Using SliderParameter Using setVariable Simulator Digital Simulator Variables Initialize Tracking Memory activity Using RegEx to get list of memory Using Arrays in Memories Accessing same Memory from multiple parts of the model Reusing Hierarchical instance with memory definitions Accessing local memory from elsewhere in the model Using Memory reference in Virtual Machine and Processing blocks Read_Memory and Write_Memory - Demo Models RD_WR_Memory - Demo Models Hierarchical Blocks Hierarchical_params Creating Multi-Instances Model Using DS_To_Instance Using Case Creating 100 Instances Using Multi-Instance Bank of N Counter model using Dynamic Instantiation Large System Example using Dynamic Instantiation Large System Modeling using Dynamic Instantiation FSM Bouncing Ball Model Modal Model Alternating Bit Protocol (ABP) Model SchmidtTrigger Model Utility Tracking Memory using Memory_Dumps and Memory_Monitor Unit- How to use

Traffic

Clock Clock Model PoissonClock Model Pulse Model Ramp Model Sinewave Model SequentialClock Model VariableClock Model Event Using Initialize File Import Reading Files Reading input from file using Traffic_Reader for Trace File input File Path format for File Reader File Path format for Traffic_Reader Interactive EventButton Model Interactive Shell Model Sketched Source Model Traffic Define Data Structure Ways to create traffic- Distribution, Triggered, Trace and Sequence Distribution-based Sequence-based Sequence-based with one field containing Data Structure Multiple threads of concurrent traffic Event-based Traffic Generator File Path format for Transaction_Sequence Delay Using Delay

Results

PlotManager Using PlotManager 3D Interactive Creator FurutaPendulum Helen Pendulum Solar System Sticky Masses Universe Plotter Using TimeData_Plotter File Path Format for TimeData_Plotter XYPlotter File Path format for XY_Plotter Using DS_TimeData_Plotter File Path format for DS_TimeData_Plotter Using DS_XY_Plotter File Path format for DS_XY_Plotter Histogram File Path format for Histogram Plotter Customize the plot for waveform viewing Using Concatenation for directory name entry Create custom XY plotters Computing Latency Computing Throughput Generating statistics for specific data transfers Write Statistics to file Create custom XY plotters Statistics Generator Resource Statistics Generating Statistics for Resources- Queues and SystemResource Generating Statistics for Resources- Event Queue Generating Statistics for Resources- Timed Queue Profile Statistics Using Statistics Blocks- Stats-Difference_of_Ports, Stats-In_Memory, Stats-Using_Probability, Stats-Cumulated_Values Text Text_Display(Buffered) File Path format for Text Display (Buffered) Text_Display(Non-Buffered) File Path format for Text_Display (Non-Buffered) Writing to a File ABS Model using Simulation Time Monitor

Behavior

Database Field Match: Lookup; Write or add to the table;and Remove from the table Using file as table entry Match all rows in the table Routing Using DB Using different file and file paths- xml csv txt File Path format for Database Processing Using different data types Define transaction attributes and randomizing attributes Using Arrays in transaction flows Searching arrays for Routing or other decisions Expression List or Decision Creating logic IN Using IN OUT Using OUT Basic Processing Using Case_Switch Using If_Else and Statement Using Select and Insert Using Statement_Delay Using While Virtual Connection Virtual Connection Model Using RegEx function to get list of virtual connections Script (Virtual_Machine) Basic Script Functions Using Self Start in Script Adding Switching in Script Extended Script Functions Using Script for Request Ack operation Fragmenter Simple Clock Shifting Simple Clock Shifting Using Event Simple Script Counter Multi-Thread Script_Processor,Cache and DRAM Script_Scheduler Ring Topology with 8 cores Script_RTOs plus Processor Using Script Profiler Virtual_Machine_Untimed Untimed Virtual Machine

Delay and Utilities

SingleEvent Using SingleEvent Fork or Isolate Input Using Isolate_Input Join or Isolate Output Using Isolate_Output Execution Control Switching Ordered Merge Switch Switch Commutator Persistent Switch Boolean Trigger

Resources

Smart Resource/Queue/Server Resource Single Smart_Resource Queue Multiple Queues with Smart_Resource for Pop and Arbitration Arbitration between Resources Smart Resources working with Virtual Machine Using Smart_Timed_Resource Array of Arbitration Using getBlockStatus for Queue and Server Channel and Pipeline Video Cache Paging Model using Channel Using getBlockStatus for Channel_N Event Queue Using All Queues Using Copy, Set and Length Viewing Rejected/Dropped Data Structure Generating Statistics Quantity-based Using QS Queues Viewing Rejected/Dropped Generating Statistics Timed_Queue Using Timed Queues Viewing Rejected/Dropped and current Queue length Generating Statistics Server_N Model SystemResource/SystemResource_Extend/Scheduler SystemResource usage- FCFS SystemResource usage- FCFS with Preemption SystemResource usage- Round-Robin SystemResource- Hierarchical Mutual Exclusion using SoftwareMapper block Map flows to separate Schedulers(Threads or RTOS) and send to single hardware resource as a Scheduler Extending the SystemResource_Extend Access SystemResource RegEx in Script, ExpressionList blocks Single Task to Multi-Core Model Description Using getBlockStatus for SystemResource

Mapper

Mapping SystemResource usage- FCFS using Mapper SystemResoure usage- FCFS using Advanced Mapper Co-Processor model with Software Mapper

Power Modeling

PowerTable Schedulers-based system model: This is a Dynamic Voltage Frequency Scaling (DVFS) model. Look at the power information table, use of the power RegEx functions to change the state and the power levels. System and Environment Model: The power handling is done entirely using the Power RegEx functions in the Processing blocks. Look at the (1) check for current battery power, (2) charge the battery, and (3) determine scheduler on/off based on available charge. Platform Architecture model: You can evaluate the system power consumption on the software task processing. The Power table is constructed with information in the ARM datsheet. This has a complete platform including the ARM9, AHB bus, cache, DRAM and DMA controller. The power estimate can be used to partition the tasks into software and hardware; configure the devices; allocation of data to memories and optimize the platform topology Exploring Power Management Schemes: In this model, you will see how to setup scenarios, evaluate different sleep modes, modify transition cycles. If you are going to be studying power management or closed-loop voltage control at the system-level, this would be the model to look at. This model is focus on low power application. Distributed system power: In this model, we show the complete power flow- generator; consumption by mechanical, electrical and electronics; management; and conservation. Semiconductor Power: This shows how a centralized management system changes the state of all the devices. The explanation is on this page- Semiconductor Demo. Software Tasks: Shows the use of the Power modules for evaluating the hardware and software architecture for power. Simple Power: Simple model showing the use of all the power blocks. Power Analysis Tutorial: Example showing the use of equations, dynamic changing of states and frequency modification. This model is implemented at a much lower of abstraction that the other models. The description is on this Page. Hybrid System Power Design: This model looks at the end-to-end power systems- generation, consumption, management and measurement. It also utilizes the blocks available in the Power folder. This model also contains electrical, electronics, mechanical and electro-mechanical components. The model has multiple sources of power being generated. Using Power Blocks: This is model that explains the use of all the blocks in the Power folder. Battery BatteryProfile File: text file containing battery parameters and values for each type battery type. Custom battery type can be constructed by filling the resective entries. Server Model: This model contains a single Server Block. Power consumption is captured using the VisualSim power toolkit. SystemResource Model: This model contains a systemResource to which transactions are mapped from three mapper blocks. Power toolkit includes Battery, PowerTable and energy harvester. Sensor Model: This model contains application sensor traffic, architecture platform DMA channel etc. Power consumption is captured using PowerTable, Battery. SystemResource_3_Load: This model contains 3 SystemResource blocks. Each SysteResource has different power levels. This model includes energy harvester, Battery and PowerTable. Processor Model: This model contains the the processor, bus and an SDRAM. the system is powered by by a Li_ion battery which is powered by a constant power supply.

Hardware Setup

Architecture Setup Architecture Setup Utility DeviceInterface Clock Tree 4 LUT Register_N Model Register_Expr_N Model Timing Diagram USART VCD Write Using Virtual machine to create Fragment and Defragment

Processor Generator

Core Architecture Instruction Setup Basic Processor Model Using the Registers Multi-Thread Processor Multi-Core Processor Multi-Processor Shared Cache Co-Processor Model SIMD Processor Model MIMD Processor Model Processor External Definition Model Processor to External Scheduler Model Simple Cache and DRAM Model Mapping using DeviceInterface Using TaskGenerator to generate profile-based synthetic instructions for the Processor Using existing assembly sequence from annotate C-code Creating and sending Transactions Changing the Clock Speed Using multi cycle delay for the flush Processor Preemption- A Example Template Vendor Specific Processors Dual ARM_Cortex_A9 ased SoC Intel_ATOM PowerPC PowerPC750 PXA320 RAD750 Cache Cache: Cache and DRAM CycleAccurateCache: I1, D1, L2 Cache Memory Hierarchy to Memory Controller and DRAM

Memory

Memory DRAM Flash Disk Using Memory Controller Model Hardware Memory controller and DRAM Model Creating a Multi-Bank Memory Controller using statistical traffic input Memory Controller- variable data size for Read Memory Controller- variable data size for Write Memory Controller- variable data size of Read followed by Write Memory Controller- variable data size of Write followed by Read.

Hardware Devices

Bus Switch Control Defining Shared Bus with Read Transaction Defining Shared Bus with Write Transaction Linear Bus with Custom Arbitration Bus-to-Bus using Bridge Linear Bus with Retry- Read DMA - Direct Command DMA - From external device DMA - From Processor block Request-Acknowledge Bus Blocking Channel Switch Model Bridge Model Non Blocking Channel Switch Model Serial Switch

Interfaces and Buses

Standard Bus AMBA AHB Bus Model AMBA AHB MultiMaster Fabric Model AMBA AHB Bus - Retry Case Model AMBA AHB Bus - Buffered and Non-Buffered Model AMBA AHB With APB Bus Model Multiple AHB Bus Model PCI Bus Model- First Come-First Server PCI Bus Model- Round-Robin PCI Bus with Preemption Model AMBA AHB to PCI_X Bus Model CoreConnect Bus - (Read operation) Request_Acknowledge Node Model CoreConnect Bus - (Write operation) Request_Acknowledge Node Model CoreConnect Bus - (Read & Write operation) Request_Acknowledge Node Model Emerging Bus Standard AMBA AXI Single AXI Bus Model Multiple AXI Bus Model AMBA AXI - AHB Bus Model PCIe PCI Express Bus Model PCIe Bus - Two Masters with Single DRAM Read/Write operation. PCIe Bus - Two Masters and two DRAM Read/Write Operation. PCIe Bus - Two Masters and HWDRAM Read/Write Operation. PCIe Bus - Two Masters and two HWDRAM Read/Write Operation. PCIe Bus - Four Masters With Single Slave Read/Write Operation. PCIe Bus - Processor with DRAM Read Operation. PCIe Bus - VM with DRAM Read Operation. PCIe Bus - PCIe with DMA Read/Write Ope.ration. PCIe Bus - Tweleve Masters and Twelve Slaves Read/Write Operation BackPlaneBus PCI Bus Model RapidIO Rapid IO System Model RIO with Two Masters and One Slave Device Read/Write Operation RIO with Two Master and Two Slave Devices Read/Write Operation RIO with Four Master and Two Slave Devices Read/Write Operation RIO with DMA and DRAM Switched Ethernet Switched Ethernet Spacewire Spacewire System Model Spacewire Multi-Router Model FibreChannel FC with Single Switch FC with Two Switches FC with Multi-Switch FC with 96 Node Switch FireWire FireWire Demo Model TTEthernet TTE Model with Redundancy TTE Model with Coldfire Processor TTE Model with 8 senders and 3 listeners with 2 bridges TTE Model with 3 senders and single listeners with 4 bridges TTE Model with two senders and one listener AFDX AFDX System with Single Switch and Four End Systems AFDX System with Two Switches and Eight End Systems Audio Video Bridging Multi-Node AVB System- Demo Model Multi-Node AVB System with Bridge- Demo Model Large AVB Network using Dynamic Instantiation- Demo Model Autosar Autosar WatchDog Manager with ECU Network Fault injection test model Autosar ECU Node Processor Model CAN Bus Can bus with Ethernet Gateway Multiple CAN Segment with CAN Ether Switch 8 Node CAN Bus Model FlexRay FlexRay Demo model FlexRay 16 Node Network

FPGA's

Xilinx FPGA Microblaze: Simple model showing the usage and construction Microblaze-based system: Combines the Linear Memory Bus and Hardware Accelerators Xilinx e405 Platform with AHB Bus Model Virtex 4-PCI-to-Memory: Combines PCI, Ethernet, CoreConnect, DRAM, PPC405 Virtex 4-CoreConnect: Combines PCI, Ethernet, CoreConnect, DRAM, PPC405 Virtex 4-MPMC2: Combines PCI, Ethernet, MPMC2, DRAM, PPC405. Reads operations only Zynq 7000 All Programmable SoC Model Demo Model1 Demo Model2 Demo Model3 Xilinx FPGA Interface: Simple model showing VisualSim interface with Xilinx FPGA Description Note: To successfully interface with Xilinx FPGA user requires additional configuration files, please contact your Mirabilis Design Representative

System Language

C_and_CPP Custom Slave- Cycle-accurate and TLM Integer Array Flip Flops Accessing multiple Procedures Transmitting Record Token Using Short data type Splitter Decision-based model Input and Output Struct Master-Bus-Slave Using Application_Interface- Using the Application Interface Block Using different data types on the Input and Output Interfaces- Using the Application Interface Block MatLab Continuous Time MatLab Processing Expressions in MatLab Multiple Output ports and parameters Using the fields of the input Data Structure with a MatLab function Using fields of the Data Structure incorrectly Open Simulink Model Python Ptolemnizer Model Compare Python Model and a VisualSim block version of a Scale function Satellite Toolkit STK Multiple Command Example

Hardware Language

SystemC TLM2.0- Timed Model with VisualSim Master, VisualSim Slave, TLM Slave TLM Bus and TLM Master Multiple Counters in a Sequence Simple Bus Model Simple Bus Model with custom VisualSim Master TimedPIPE with all SystemC Components Timed PIPE Decoder and NAND XOR Fixed Width Verilog Binary Decoder (Windows) Binary Decoder (Linux) Full Adder (Windows) Full Adder (Linux) Half Subtractor (Windows) Half Subtractor (Linux) Multiplexer (Windows) Multiplexer (Linux) Oscillator Counter MPMC

Data Access

Corba Corba Model SQL Database InteractiveQuery Database Model File_Access File_Reader Traffic_Reader File_Writer Socket Datagram Counter Model Datagram DE Model Datagram Injector Model Datagram Parsed Model Datagram UnParsed Model Serial_io Serial_IO Model (Currently not available. Contact Mirabilis Design) Excel Simple Excel Interfacing Model DS to CSV Model XML_Parsing Simple XML Parsing Model

Math Operations

Array ArrayAppend Model ArrayAverage Model ArrayElement Model ArrayExtract Model ArrayMaximum and Minimum Model ArrayPeakSearch Model ArraySort Model Boolean BooleanSelect Model BooleanSwitch Model Counter Counter_Basic Model Counter_Loop_K Model Counter_Loop_Port Model Counter Model Distributions ColtRandom Model Logic Math_and_Trig Absolute Value Model Remainder Model Parser Transform BitsToInt Model ArrayToElements Model ArrayToSequence Model ElementToArray Model SequenceToMatrix Model String Operations

Applications

Auto Multi-Protocol- CAN and Ethernet with a Gateway Description CAN bus with Bridge to Ethernet CAN Bus With Error Frames CAN Bus with Overload Frame CAN Bus with RTR Enabled FlexRay blocks usage Autosar block usage- with C-code Autosar block usage without C-Code AVB- Audio-Video Bridging AVB Example- How to use the AVB library blocks AVB Dynamic Instantiation- How to create large AVB Models with multi-domains. AVB Ethernet Only- Using the AVB blocks with Ethernet streams only AVB Multi-Bridge- Connecting the Nodes via multiple Bridges AVB Latency Excel- Writing the latency statistics to Excel AVB Latency Plot- Generating a custom latency plot AVB Latency Stats- Generating the latency statistics for a stream AVB Stream Plot- Generating the latency for a single stream using the AVB_Stats block Aerospace TTEthernet TTE Model with Redundancy TTE Model with Coldfire Processor TTE Model with 8 senders and 3 listeners with 2 bridges TTE Model with 3 senders and single listeners with 4 bridges TTE Model with two senders and one listener Spacewire Spacewire System Model Spacewire Multi-Router Model Networking Other Network Block Using Ethernet Traffic Generator- Using the Traffic Generator to generate Ethernet streams Retry_Layer1 Demo Model shows the connection between the Layers and to the Node. It also shows the association of the Layer_Table to the Layer_Protocol. This models shows the use of multiple Layer_Tables in the model and the setting of the retry. Network_External_Defn Demo Model shows the Configuration Layer setting to External Delay and the conenctivity for this. Network_Basic Demo Model. This shows a basic connectionless network, the Routing Table reference and the path definition in the Database block. Retry Network Demo Model. This shows a Connected Network with the layers of the OSI stack referenced. Gateway_Connected Demo Model. This shows the use of the Node as a Gateway. Multi_Network_w_Intermediate_Gateway Demo Model. This model has a intermediate of Gateway nodes. Gateway_w_Diff_Return_Model Demo Model. In this model, the forward and return directions use a different Gateway Node. Two_Networks_w_Gateways Demo Model. This shows two Gateways between two networks. Using Multicast Demo Model. This models uses the Multicast block to create a multicast and a broadcast. Header Compression: Evaluate different TCP/IP Header Compression algorithms Wireless_Sensor Antenna Pattern: This example illustrates modeling transmit antenna gain. The Sender has an 8-element beamforming antenna with a steering angle applied. When you run this model, the Receiver will move around the Sender and measure the received power. It then plots the receive power on a polar plot, with the distance from the origin representing the received power, and the angle representing the angle of its position relative to the transmitter. In effect, it measures and displays the antenna gain pattern of the Sender. (See ReceiveAntennaPattern.xml as an example of modeling receiving antenna gain) Circular Range: This model shows a transmitter (at the left) and a receiver (at the right), where the receiver moves in and out of range as the model executes. The channel is a LimitedRangeChannel, which is a simple wireless channel model where the transmitter specifies via a parameter in its output port the distance over which it can transmit. In this model, that distance is shown graphically as the radius of the circular icon for the transmitter. As the model executes, at random times, the range of the transmitter decreases. Collisions: In this model, two transmitters broadcast signals that may collide with one another. The receiver will correctly receive a signal if the signal to interference ratio is 3dB or better, meaning that the received signal has at least twice the power of the interfering signal. When Transmitter1 is far away from the receiver, it cannot interfere with the transmission of Transmitter0. However, when it gets close, it can. Evader/Pursuer: This model shows an "evader" and a "pursuer" moving through a sensor network. The "evader" emits sounds that are detected by the sensor nodes, and the sensor nodes relay information to the pursuer. Running the model shows the evader moving at random and the pursuer seeking to track it based on the information from the sensors. PowerVariability: This model shows a transmitter (at the left) and a receiver (at the right), where the receiver moves as the model executes. The channel is a PowerLossChannel with a limited range. When the receiver is in range, the power depends on the distance to the transmitter, according to an inverse square law. Small World: This demo shows a sensor network where each node rebroadcasts the first message it receives. An "initiator" component broadcasts a message, and the model keeps track of the number of nodes that receive the message after one hop, after two hops, etc., and plots a histogram. Smart Parking: Sensors placed in a parking lot can be used to collect data (including which parking spot is taken, how long a car has parked on a spot). The parking lot can process the collected data and provide some services to clients to guide their parking. This demo illustrates these ideas. The dots are sensors on the parking spots. We use green color to indicate the spot is free and red to indicate the spot is taken. When a sensor detects a car arriving or leaving a spot, it sends an update to the server of the parking lot, which collects and processes sensor updates to provide information to parking clients. The "car model" component models when a car arrives or leaves, and where to park based on the information the server provides. It is a abstraction for all the cars dynamics during a specific time. The components in the upper right corner represent the server function, which receives sensor data and provides information the clients. The "signal light" component indicates whether the parking lot is full (using red) or not (using green). Terrain Model: This simple example illustrates modeling terrain effects. The TerrainProperty models some obstacle which blocks the communication from the Sender to the Receiver if the communication path between them intersects with the terrain shape. When you run this model, the sender will emit a signal every second from time 0.0 to time 36.0. The Receiver will move around the Sender and measure the received power. It then plots the received power on timed plot if it is greater than 0.0. The plot shows that the receiver can only receive the signal (with power value larger than 0) when it is not shadowed by the terrain model. Sound Detection: This example shows a SoundSource (concentric circles icon) moving through a field of sensors (SoundSensor actors, with translucent circle icons) that detect the sound and communicate with a Triangulator actor (overlapping ellipses icon). The Triangulator performs sensor fusion to triangulate the location of the sound source. It generates a plot with estimated locations.

Algorithmic

Analog Mixed-signal model of a MEMS accelerometer Square-Wave Model Switch Model Control_Systems Blending Controller Car Tracking Model Helicopter Model Level Crossing Detector Lorenz Model Thermostat Model Transmission Model Image_Processing Note: Requires Java Advanced Imaging and Java Media Framework Libraries DCT Model HTVQ Model Complete list of Image Processing Examples Petri_net Signal_Processing Butterfly Model Convolutional Coder Eye Model Fixed-Point FIR Model Fixed-Point Model Least Mean square adaptive filter Model Maximum Entropy Spectrum Model Rijndael Encryption Model simple Periodogram spectral Estimation Model Voice analysis/synthesis algorithm Model ViterbiDecoder Model

Library Model

Demonstration Models and Example Systems

Basic Graphical Operations

RegEx Function

Draw Tools

Parameter

Simulator

Variables

Hierarchical Blocks

FSM

Utility

Clock

Event

File Import

Interactive

Traffic

Delay

PlotManager

3D Interactive Creator

Plotter

Statistics Generator

Text

Database

Processing

Expression List or Decision

IN

OUT

Basic Processing

Script (Virtual_Machine)

Virtual_Machine_Untimed

SingleEvent

Fork or Isolate Input

Join or Isolate Output

Execution Control

Switching

Smart Resource/Queue/Server Resource

Channel and Pipeline

Event Queue

Quantity-based

Timed_Queue

SystemResource/SystemResource_Extend/Scheduler

Mapping

PowerTable

Battery

Architecture Setup

Utility

Core Architecture

Vendor Specific Processors

Cache

Memory

Bus Switch Control

Standard Bus

Emerging Bus Standard

Xilinx FPGA

C_and_CPP

MatLab

Python

Satellite Toolkit

SystemC

Verilog

Corba

SQL Database

File_Access

Socket

Serial_io

Excel

XML_Parsing

Array

Boolean

Counter

Distributions

Logic

Math_and_Trig

Parser

Transform

String Operations

Auto

Networking

Wireless_Sensor

Analog