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Home | Demonstrations | Computing | L1,L2,L3 Cache - Queuing Model

      L1,L2,L3 Cache - Queuing Model


Performance Modeling of Cache Structure

VisualSim provides a graphical environment to design the cache hierarchy that will best match the requirement of a particular application. The analysis can be performance at various level of abstratcion depending on the analysis requirement. This model generates requests from the processor at a fixed CPI (cycles per instruction). These are sent through the hierarchy. The user can set the cache hit-ratio to 1.0 and this will be highest level of cache. Using a cache-hit ratio for each stage, an evaluation is performed to compare utilization and response times for various cache speeds and target cache-hit ratios.

The VisualSim model associated with this description is provided below. You can view, change parameter values and run simulation right from within the Web Browser. No additional software is required. This shows how you can use a pre-built VisualSim model for doing trade-studies.

To use the models at the links, click on the GO button to run the simulation. Double-click on any parameter in the model window to change the parameter value.

Click here to view and execute the VisualSim model

VisualSim is a performance analysis, power estimation and architecture exploration environment for systems, SoC, FPGA and real-time software design. The fully graphical modeling and simulation environment can be used by designers to quickly capture a model of their proposed system, conduct trade-studies and develop a highly optimized specification that meets the end-customer requirements. The environment provides a complete modeling library and automated statistics generators for occassional to seasoned designers to get their designs done quickly and accurately. As 90% of the product cost and performance are derived during the early R&D stage, success and failure is determined by understanding the traffic and resource requirements of the proposed solution.

The model is created using a standard flow of data model. The traffic generator in the Processor generates traffic based on a uniform random distribution. The caches are all identical in model. The latency and queuing are modeled as a FCFS resource, a standard block in VisualSim. The hit-miss decision is based on a random distribution using the hit-ratio parameter value that is provided by the user.

This model uses 4 pre-built building VisualSim blocks to construct the whole model. The ease-of-use and the rapid learning makes VisualSim particularly suited for quick trade studies..


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